A question for the PCB gurus:

We have been receiving boards from a supplier that are exhibiting
separations at the interface between plated hole wall and internal layers
(a.k.a. interplane separations, post separations, interconnect defects) in
cross-section, after thermal stress. Specifically, the separations are
occurring between the electroless copper and electrolytic copper. Horizontal
cross-sectioning reveals that the location of the separations is consistent
from hole to hole. For example, in a grouping of holes viewed in horizontal
cross-section, the majority of holes will show the separation extending from
the 6 o'clock position to the 11 o'clock position. Any suggestions on what
process/processes the vendor should look to for troubleshooting?

Thanks,
David Smith
Benchmark Electronics

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