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April 2000

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Subject:
From:
Russ Winslow <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Sat, 1 Apr 2000 20:13:30 -0800
Content-Type:
text/plain
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text/plain (139 lines)
Jim,

Have you analyzed the data to see if some of the LCC's are worse than
others?
We are a tinning house on the West coast.  We've seen a lot of LCC's.  If
you have some suspect units send a couple to me and I'll check them for you.
(free of course)  Most semiconductor companies mark their parts after lead
tinning.  So after tinning they go through post mark cure and sometimes even
demark and remark.  They may even go into burn-in after tinning. (Ouch) In
many cases they don't even wash them after sodium bicarbonate blasting to
remove the markings.  It isn't a very nice thing to do to a shinny new lead
finish. All these steps can be detected with a discerning eye and a good
microscope.  An autopsy of sorts.  I would need components which have not
been board mounted.

Russ Winslow

Six Sigma
1940 Concourse Drive
San Jose, CA  95131

(408) 526-1350 x 1


-----Original Message-----
From: Marsico, James [mailto:[log in to unmask]]
Sent: Friday, March 31, 2000 4:22 AM
To: [log in to unmask]
Subject: Re: [TN] SMT DEFECT RATES (DPMO)


The LCCs we use are all pre-tinned.  If not received that way, we send them
out to a tinning house.
Thanks,
Jim M.


        -----Original Message-----
        From:   Misner, Bruce [SMTP:[log in to unmask]]
        Sent:   Thursday, March 30, 2000 11:52 AM
        To:     [log in to unmask]
        Subject:        Re: [TN] SMT DEFECT RATES (DPMO)

        Jim,

        I would have to agree with Ed. Pre-tinning should help immensly,
just be
        careful of leaching, although it shouldn't be a concern unless you
plan on
        recycling LCC's off reject boards.

        Bruce Misner

        > ----------
        > From:         Edward J. Valentine[SMTP:[log in to unmask]]
        > Reply To:     TechNet E-Mail Forum.;Edward J. Valentine
        > Sent:         Thursday, March 30, 2000 11:09 AM
        > To:   [log in to unmask]
        > Subject:      Re: [TN] SMT DEFECT RATES (DPMO)
        >
        > Jim - A side question - Are you pretinning your LCC's?  If not,
you should
        > seriously consider the pre-tinning operation, especially if the
Gold
        > castellations are contaminated. You would know this ahead of time
by
        > verifying the coverage after pre-tinning. And, in my experience,
the
        > pretinning produced significantly better soldering results even
though you
        > are adding additional process steps. Ed/
        >
        > Ed Valentine
        > Electronics Manufacturing Solutions
        > 8612 Mourning Dove Road, Raleigh, NC 27615
        > Phone: (919) 270-5145, Fax: (919) 847-9971
        > Email: [log in to unmask]
        > Website: http://www.ems-consulting.com
        >
        > ----- Original Message -----
        > From: Marsico, James <[log in to unmask]>
        > To: <[log in to unmask]>
        > Sent: Thursday, March 30, 2000 10:29 AM
        > Subject: [TN] SMT DEFECT RATES (DPMO)
        >
        >
        > > Dear Technet:
        > >
        > > I've been tasked by my superiors to query industry to find out
what
        > other
        > > electronic assemblers are yielding off of their surface mount
line.  To
        > > compare apples to apples, here are my specifics:
        > >
        > > We assemble SMT for military/high rel.  The majority of the
parts are
        > > ceramic leadless chip carriers  (LCCs) and ceramic chip
components
        > > (resistors, caps, diodes).  We're starting to track solder
defects more
        > > closely when the assemblies come right off the line, and we
don't like
        > what
        > > we see.  The major anomaly is insufficient solder fillet on the
LCCs.
        > > (There could be one joint insufficient out of 20. By the way,
solder
        > paste
        > > deposits are perfect!)  Whether or not these are actually
defects is
        > under
        > > discussion.
        > >
        > > What I'd like to know is:
        > > 1)      What kind of defect rates (PPM) are others, building
similar
        > > assemblies, getting from their SMT lines.
        > > 2)      Does anyone experience insufficient solder on LCCs?
        > >
        > > Thanks,
        > > Jim M.
        > > AIL Systems Inc.
        > > 631-595-5879

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