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April 2000

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Subject:
From:
"Mcmaster, Michael" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Tue, 11 Apr 2000 16:43:37 -0700
Content-Type:
text/plain
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text/plain (118 lines)
Exposed copper is inherent in boards that retain the etch mask as a surface
finish, basically reflowed tin or electrolytic nickel/gold.  These masks are
plated on top of the copper in the desired conductive pattern.  The copper
underneath is then etched away, leaving the sides of the trace exposed.  If
this is a concern, you can switch surface finishes.  For surface finishes
like Electroless Nickel/Immersion Gold, HASL, Immersion Silver, etc, the tin
etch mask is stripped off and the surface finish covers all exposed copper,
sides and top.

        Mike McMaster
        RF Product Engineer
        Merix Corporation
        503-992-4263


        ----------
        From:  Timothy Reeves [SMTP:[log in to unmask]]
        Sent:  Wednesday, April 05, 2000 12:17 PM
        To:  [log in to unmask]
        Subject:  Re: [TN] Exposed copper around the periphery of annular
pads..

        Steve, I think, looking at the pictures and based on my own
understanding of
        the spec. that exposed copper IS allowed ONLY on the vertical edges
of
        traces and pads, nowhere else (they fail to clearly state that the
vertical
        surface clause is an exception to the no exposed copper clause)
         So your boards meet the spec. It is a confusing spec, isn't it!

        > ----------
        > From:         Stephen R. Gregory
        > Sent:         Wednesday, April 5, 2000 8:55
        > Subject:      Exposed copper around the periphery of anular pads..
        >
        > Hi ya'll!
        >
        > I got called back to incoming this morning to look at a PTH board
that
        > shows
        > exposed copper, but it's only at the side edges around the
periphery of
        > the
        > anular pads...it's like this over the whole board. The top
surfaces have
        > tin/lead plating, but not the side edges.
        >
        >                             Top surface of pad is plated
        >                                                |
        >                                 ________V_________
        > __________________|__________________|__<-----Exposed copper on
sides
        >
        >                                             PCB
        >
        > Is this a defect? Looked in the IPC-A-600F on page 85, (3.3.10
Solder
        > coating
        > thickness) and there's a conflicting statement I think. It says;
        > Acceptable -
        > Class 1,2,3, "Solder coating thickness is uniform. Vertical
(conductor and
        > land) areas may not be covered. No exposed copper is evident."
        >
        > On one hand it says that the vertical surface may not be covered,
but on
        > the
        > other hand it says you can't have exposed copper. If the vertical
surface
        > doesn't have to be covered, then you're gonna have exposed copper.
So
        > which
        > is it?
        >
        > Also there's a statement at the bottom of the page that visual
        > observations
        > are made on cross sections only. I can see this with my own two
        > eyeballs...don't need a cross section to see it.
        >
        > This board is for a hi-rel product by the way....
        >
        > Thanks!
        >
        > -Steve Gregory-
        >

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