Hi Mike,

What class stuff are you working on?

Here are the specs to check out (any others guys & gals?).
IPC - 4101 Specification for Base Materials for Rigid and Multilayer Printed
IPC-A-600F Acceptability of Printed Boards
IPC-A-610C Acceptability of Electronic Assemblies

IPC - 4101 covers the nominal laminate and foil thickness.  We do buy better
than the minimum specified for some characteristics to improve yield and
manufacturability.

The surface conductor thickness should be specified on the master drawing.
That's covered in IPC-A-600 (for rev E it's Section 3.2.5 and 3.2.6. but you
want to check out the latest in rev F to see if anything changed).

The solder mask thickness might also be specified on the master drawing or
IPC-A-600 (again) has an acceptable thickness:
Class 1 - Visual Coverage
Class 2 - 0.01 mm (0.0004 in)
Class 3 - 0.0175 mm (0.0007 in)
From IPC-A-600 rev E Sect. 2.9.10

So, the solder mask plus trace height should be set in stone and might need
a waiver to change it.

Can anybody offer suggestions on improving solder paste stenciling over
rough terrain?  Does Mike need a thicker stencil, better squeegee or
something?  What's the SUV's of stencils?

Hans

~~~~~~~~
Hans M. Hinners
Materials (& Process!) Engineer
Warner Robins - Air Logistics Center/Avionics Production Division
Manufacturing Branch (LYPME)
380 Second Street, Suite 104    (Building 640)
Robins AFB, GA  31098-1638
912-926-1970 (Voice) 468 - 1970 (DSN)  912-926-7164 (Fax)
mailto:[log in to unmask]
.

> -----Original Message-----
> From: Michael Forrester [SMTP:[log in to unmask]]
> Sent: Thursday, March 02, 2000 12:20
> To:   [log in to unmask]
> Subject:      [TN] Spec for "Lumps" on PCB
>
> Our boards are primarily fine pitch surface mount.  We currently have a
> problem
> with the height of the solder mask over our via's being
> too high causing the solder stencil not to sit flat to the board.  The
> height of
> the vias solder mask included) are 4 mils higher than the rest
> of the board (including solder mask  I believe the actual problem is that
> we
> have the vias filled with epoxy and the
> height of the epoxy in relation to the top of the via pad is too high.  Is
> there
> a spec (IPC,JEDIC,MIL) that covers such an issue?  If not, what
> do others spec out to insure that there is no interference from "lumps".
> Thank
> you.
>
> Best Regards,
>
> Mike Forrester
> LeCroy Corp.
> [log in to unmask]

##############################################################
TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c
##############################################################
To subscribe/unsubscribe, send a message to [log in to unmask] with following text in
the body:
To subscribe:   SUBSCRIBE TECHNET <your full name>
To unsubscribe:   SIGNOFF TECHNET
##############################################################
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
information.
If you need assistance - contact Keach Sasamori at [log in to unmask] or
847-509-9700 ext.5315
##############################################################