Hi Ed,
You are giving us very little to go on. You do not even say whether the
"interconnects" you have problems with are SJs or PTH/PTVs.
>We had some concerns about marginal interconnects on some 10 layer boards
>that had passed the bare printed circuit board bed of nails test at 100
>volts.
This would indicate PTH/PTVs as your problems, but bare board bed-of-nails
testing does not give you any idea whether your board can survive soldering
operations.
>To instill more confidence in the products, the bare printed circuit boards
were >submitted for environmental chamber thermal stressing (the 3 cycle test
as outlined >by IPC).
What "3 cycle test as outlined by IPC" are youtalking about? I am not aware
of any such test, and I have been involved in IPC a loooooong time.
>Parts were stressed by an outside lab, returned, assembled, in circuit
tested, burned >in, then final tested. A sample of the parts that passed the
final assembly test was >sent out again for the environmental chamber stress
test.  The parts were then >retested and all the parts failed test. ( We have
not determined why yet.)
What "environmental chamber stress test"? Temperatures? Cycles? Shock?
>Based on this I have two questions.
>1) Is it possible to overstress loaded board?
Answer: Absolutely.
>2) Would you expect assembled boards to pass after chamber thermal cycling?
That all depends on the details! Properly designed and built assemblies pass
chamber thermal cycling all the time.

Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com

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