Hi all,

 I need some feedback. Here is the situation.

We had some concerns about marginal interconnects on some 10 layer boards
that had passed the bare printed circuit board bed of nails test at 100
volts. To instill more confidence in the products, the bare printed circuit
boards were submitted for environmental chamber thermal stressing (the 3
cycle test as outlined by IPC). Parts were stressed by an outside lab,
returned, assembled, in circuit tested, burned in, then final tested.

A sample of the parts that passed the final assembly test was sent out again
for the environmental chamber stress test.  The parts were then retested and
all the parts failed test. ( We have not determined why yet.)

Based on this I have two questions.

1) Is it possible to overstress loaded board?
2) Would you expect assembled boards to pass after chamber thermal cycling?
( I don't know if thermal cycling is appropriate for assembled products )

All thoughts are appreciated.

Ed Cosper
ABC

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