Jim - A side question - Are you pretinning your LCC's? If not, you should
seriously consider the pre-tinning operation, especially if the Gold
castellations are contaminated. You would know this ahead of time by
verifying the coverage after pre-tinning. And, in my experience, the
pretinning produced significantly better soldering results even though you
are adding additional process steps. Ed/
Ed Valentine
Electronics Manufacturing Solutions
8612 Mourning Dove Road, Raleigh, NC 27615
Phone: (919) 270-5145, Fax: (919) 847-9971
Email: [log in to unmask]
Website: http://www.ems-consulting.com
----- Original Message -----
From: Marsico, James <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, March 30, 2000 10:29 AM
Subject: [TN] SMT DEFECT RATES (DPMO)
> Dear Technet:
>
> I've been tasked by my superiors to query industry to find out what other
> electronic assemblers are yielding off of their surface mount line. To
> compare apples to apples, here are my specifics:
>
> We assemble SMT for military/high rel. The majority of the parts are
> ceramic leadless chip carriers (LCCs) and ceramic chip components
> (resistors, caps, diodes). We're starting to track solder defects more
> closely when the assemblies come right off the line, and we don't like
what
> we see. The major anomaly is insufficient solder fillet on the LCCs.
> (There could be one joint insufficient out of 20. By the way, solder paste
> deposits are perfect!) Whether or not these are actually defects is under
> discussion.
>
> What I'd like to know is:
> 1) What kind of defect rates (PPM) are others, building similar
> assemblies, getting from their SMT lines.
> 2) Does anyone experience insufficient solder on LCCs?
>
> Thanks,
> Jim M.
> AIL Systems Inc.
> 631-595-5879
>
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