Subject: | |
From: | |
Reply To: | DesignerCouncil E-Mail Forum. |
Date: | Thu, 30 Mar 2000 11:08:48 -0800 |
Content-Type: | text/plain |
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Tom,
This is very informal, but the smallest via hole I use to keep the cost
down, is 12 mil w/ 24 mil pad. On vias smaller than 16 mil I pretty much
always allow +.003/-.012.
Richard
> -----Original Message-----
> From: Frayda, Tom [SMTP:[log in to unmask]]
> Sent: Thursday, March 30, 2000 6:19 AM
> To: [log in to unmask]
> Subject: [DC] signal via padstacks
>
>
> I would like to take an informal survey of what folks are commonly
> specifying for standard signal via padstacks for 0.062" thick, 1 oz
> copper, 2-4 layer boards.
>
> I am in the process of revamping our decal libraries to comply with
> IPC Level B producibility (as much as realistically possible) and am
> troubled by the 0.013" +/-0.003" Dia. finished hole / 0.025" Dia. pad that
> was specified by my predecessors. This doesn't even meet Level C and I am
> concerned about the possibility of breakout. However, to the best of my
> knowledge, breakout with these vias has not been a problem in the past.
>
> Also, since this via is currently being used, I do not want to
> increase the pad size, but would rather decrease the finished hole size.
> What is the minimum finished hole size that won't drive up the cost with
> your particular fabricator?
>
> Your comments on this would be appreciated.
>
>
> - Tom
>
>
> *******************************************
> Thomas A. Frayda, C.I.D.
> PCB Designer
> Detection Systems, Inc.
> 130 Perinton Parkway
> Fairport, NY 14450-9199
> www.detectionsys.com <http://www.detectionsys.com/>
> www.dsworld.com <http://www.dsworld.com/>
> TEL: 716-223-4060 x4365
> FAX: 716-421-4263
> E-mail: [log in to unmask]
> <mailto:[log in to unmask]>
> *******************************************
>
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