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Tue, 14 Mar 2000 10:52:24 EST |
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Hi ya'll!
I gotta board here that has a problem with the traces, it looks something
like this:
Nick in the Trace
|
V ___
________________ ___,/ \
\_/ | <-------This is supposed to
be a via..
______________________, |
\___/
(I hope my "ascii cad" conveys what I'm trying to show) Reading the
IPC-A-600F at 2.10.1.1 Conductor width it says for class 2 and 3 it is
acceptable when;
"Any combination of isolated edge roughness, nicks, pin holes, and scratches
exposing the base material that reduces the conductor width by 20% of the
minimum value or less."
So I'm reading this correctly, if the nick reduces the trace width by more
than 20% of the overall trace width, it is a reject...right? This "nick"
seems to have been etched like this...it's at the same place on the same
board that's in a 4-up panel. The other 3-boards in the panel don't have this
"nick". Booger on the artwork or something huh?
Just want to be sure...
-Steve Gregory-
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