I totally agree with Dave and Larry that solder paste selection is the first thing one should look at when investigating voiding for any part type, but especially BGAs, QFNs, and larger SMT caps and resistors. Some pastes are much more prone to excessive voiding than others.
You should also review your paste handling procedure, including the time out of refrigeration, using sealed tubes or syringes rather than jars, never re-refrigerating any paste that has reached room temp, etc, etc.
But one thing I want to stress is that as Dave pointed out, there are no "requirements" for QFN voiding, only guidelines. I personally have never seen a design where the minimum heat transfer did not occur due to excessive voiding, but if it did it was because the original design did not take at least a 50% voiding factor as part of the thermal calorie dissipation calculation or for current carrying capacity.
The other thing, some amount of voiding seen in X-rays is a GOOOOD thing, as Martha said. It shows you have a good solder joint connection between the bottom of the part and the pad on the PWB.
I have seen engineers do all kinds of window panes, aperture reductions, etc., to reduce voiding and gain a totally "opaque" solder joint, only to find the lack of voids was due to no solder connection whatsoever between pad and part! But they didn't figure that out until later, when it was too late.
dean
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Larry Dzaugis
Sent: Monday, January 08, 2018 11:04 AM
To: [log in to unmask]
Subject: Re: [TN] solder voids - QFN belly pad
The requirements may include heat transfer This was a critical specification and drove everything for high current products.
I have had spec's as tight as 10% or less voiding with a Cpk of better than 1.67.
This results in average voiding less than 5%.
It takes design, equipment, materials and process to achieve this on a 1mm thick copper and 1.5 mm Al and Fr4 PCB's.
Digital applications that did not require heat transfer, were 50% and some application satisfied with a ground connection.
Unfortunately, solder paste selection may be forced on you rather than selecting one that optimizes low voiding.
On Mon, Jan 8, 2018 at 11:41 AM, David Hillman < [log in to unmask]> wrote:
> Hi Guy - can you define "excessive"? Currently the IPC-JSTD-001 has no
> requirement for center pad voids. The IPC-7093 specification contains
> guidance that the maximum voiding for the center pad should be 50%.
> There is a IPC-JSTD-001 task group looking at the topic as there has
> been significant discussion on what the maximum void value should be
> and what the current published technical data supports. I can tell you
> that most of the issue isn't solder joint reliability but component
> functional issues which is a design component selection attribute and
> not a process attribute. With that being said, the solder paste
> formulation has a huge impact on the creation of voids provided you have addressed the "open via"
> influences. Take a look at the 2017 SMTAI paper APT5.2 by Richard
> Coyle, it will be very useful in your discussions.
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
>
> On Mon, Jan 8, 2018 at 10:26 AM, Guy Ramsey <[log in to unmask]> wrote:
>
> > We are having trouble with a lot of boards.
> > We are seeing excessive voids like the ones on page 18 of this
> > presentation.
> >
> > https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=
> > 0ahUKEwj27JnJ38HYAhUF5YMKHWYICvcQFggpMAA&url=https%3A%2F%
> > 2Fwww.eptac.com%2Fwp-content%2Fuploads%2F2012%2F06%2Feptac_
> > 07_18_12.pdf&usg=AOvVaw2OX6J_YRqkuNUNNgDBvmwZ
> >
> >
> > The vias are filled and plated. Anyone seen this, resolved it?
> >
> >
> > Guy
> >
>
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