the important fact was the customer recognized and spefcified the
requierment. if it was a requirement that showed. Up later, it is a
problem. heat and power surge requiements

On Saturday, December 21, 2013, Reuven Rokah wrote:

> Yes, there are customers with less than 10%, using vapor phase soldering
> with vacuum...
>
>
> On Sat, Dec 21, 2013 at 1:34 AM, Bev Christian
> <[log in to unmask] <javascript:;>>wrote:
>
> > I don't have our company standard in front of me, which I helped write -
> > but
> > can't remember the particulars right now.  Old age?
> >
> > Anyways OUR designers wanted a max of FIFTEEN % voids under PA QFNs.  We
> > wanted to tell them where to go, but decided just to whisper at the
> walls.
> > That being said, we knew getting there would be really, really tough in
> > some
> > instances.  We made a distinction between power QFNs and others and where
> > the voids sat in reference to the actual silicon chip.
> >
> > Joyce,
> > Did I get that last bit right?
> >
> > Bev
> >
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]] On Behalf Of Reuven Rokah
> > Sent: Friday, December 20, 2013 3:23 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of QFNs
> >
> > Thanks Dave,
> > I hope the committee will consider it in the next revision.
> >
> >
> > On Fri, Dec 20, 2013 at 10:03 PM, <[log in to unmask]> wrote:
> >
> > > Hi Reuven - while I whole heartedly agree that it would be much easier
> to
> > > do, how are we going to list a component specific function in the
> > JSTD-001?
> > > That list of components would be a mile long and ten feet deep. The
> > > JSTD-001/IPC-610 contain requirements and criteria that are applicable
> to
> > > classes or groups of component technologies. The 40% maximum void
> > criteria
> > > does not apply to all QFN style components so its inclusion would
> benefit
> > > some users but not all users which is a condition that the committee
> > > avoids. It would be great if the JSTD-001/IPC-610 specifications would
> > take
> > > care of all of the component issues but there are some
> > > requirements/criteria which are design/component specific which are
> what
> > > drawing notes are intended for.
> > >
> > > Dave
> > >
> > >
> > >
> > > From:        Reuven Rokah <[log in to unmask]>
> > > To:        [log in to unmask]
> > > Cc:        TechNet E-Mail Forum <[log in to unmask]>
> > > Date:        12/20/2013 01:51 PM
> > > Subject:        Re: [TN] IPC-A-610E, Voids in Thermal exposed pad of
> QFNs
> > > ------------------------------
> > >
> > >
> > >
> > > Agree,
> > > It will be easier to define in the SOW (Statement of Work) the required
> > > percentages in accordance with IPC class 1,2 or 3.
> > >
> > >
> > > On Fri, Dec 20, 2013 at 9:37 PM,
> > <*[log in to unmask]*<[log in to unmask]>>
> > > wrote:
> > > HI Reuven - If the QFN component has specific thermal dissipation or
> > > electrical grounding requirements, then the customer is leveling the
> 25%
> > > maximum void requirement for a data driven reason which is how we want
> > such
> > > requirements to be determined. Not all QFN or BTC components have those
> > > specific physical requirements.
> > >
> > > Dave
> > >
> > >
> > >
> > > From:        Reuven Rokah
> > <*[log in to unmask]*<[log in to unmask]>
> > > >
> > > To:        *[log in to unmask]* <
> [log in to unmask]>
> > > Cc:        TechNet E-Mail Forum <*[log in to unmask]* <


______________________________________________________________________
This email has been scanned by the Symantec Email Security.cloud service.
For more information please contact helpdesk at x2960 or [log in to unmask] 
______________________________________________________________________