WHAT CAUSES WARPAGE?
     
        Warpage has many possible sources. One of the most
     common sources is odd layer numbers requirements that cause
     dissimilar differences in lay-up/construction balance. i.e.,
     on a 9 lyr board. To make this PCB a fabricator would
     require to use 4 double sided cores and 4 B-stage or prepreg
     locations. This would have a double sided core on one side
     and a copper foil on the other. (See diagram)
     
                      ///////////// L1
                   ___///////////// L2
                  |   \\\\\\\\\\\\\ L3
                  |___\\\\\\\\\\\\\ L4
           PREPREG|   ///////////// L5  <CENTER OF STACK
         LOCATIONS|___///////////// L6
                  |   \\\\\\\\\\\\\ L7
                  |___\\\\\\\\\\\\\ L8
                      ============= L9

        During the lamination task there is an expansion and
contraction that takes place. The prepreg, being semi-cured,
has a tendency to see more of this movement. Since the above
lay-up has the outside of the board with a core on one side
and a copper foil on the other, there would be a greater
chance of warpage due to the center of the stack location
being layer 5. This type of board does not match material
type evenly from side to side as you move out towards the
outside of the package. This stack would have the outermost
core being more package dominant and would tend to bow
towards the layer 9 side.

        If a redundant plane (Power or Ground) could be added
to the package to make the stack a 10 layer, we would have
an even material type on each side of the center of the
stack.  (See diagram)

                   ___ ------------ L1
                  |    //////////// L2
                  |___ //////////// L3
           PREPREG|    \\\\\\\\\\\\ L4
         LOCATIONS|    \\\\\\\\\\\\ L5
                  |---                  <CENTER OF STACK
                  |    //////////// L6
                  |___ //////////// L7
                  |    \\\\\\\\\\\\ L8
                  |___ \\\\\\\\\\\\ L9
                       ------------ L10

        Some other PCB parameters that can additionally impact
the flatness of the PWA are keeping copper layer types also
balanced from the center out. e.g., signals and planes also
copper thickness must also be considered. (1 oz vs. 2 oz)

        The board designer should look at his design
additionally from the stand point of board copper density.
Signals that have hardly any copper with other signal layers
that may contain a lot of circuitry routing can effect
warpage. By trying to evenly balance copper density from the
center of the package along with the horizontal center of
each layer.

        In the case of analog and digital sharing board
halves (side by side) I have seen the additional plane
shielding effect the warpage because the other portion of
the PCB didn't have it. Each thermal excursion causes
expansion and contraction and the copper areas act as a
compliant layer that holds the surrounding materials more in
place. Even copper distribution produces the best results
because each side is balanced and equally moves together
producing a flat PWA.


(I hope my futile attempts at ASCII art are legible)

Dave Hoover
Hadco Tech Center Two 

[log in to unmask] (Internet)
 
 


______________________________ Reply Separator 
_________________________________
Subject: BALANCE Cu Construction
Author:  [log in to unmask] at SMTPLINK-HADCO
Date:    1/25/96 7:11 PM



I have a Drive circuit; 2 main partitions. One is a control circuit, the other 
is an output stage that is driving power. The current in the drive stage 
is substantial and on several channels. The current on the control partition 
is low.

Consequently, I have the top half of the card with relatively low Cu density, 
and the other 'loaded' to cover my power. I need to control 'warp and twist' 
on this PWB and am concerned about the Cu distribution. I am not certain about 
how this is done with a strucure like this. What is the mechanism 
for warping a card?  I don't neccessarily wan't to load up the layers with 
Cu to balance the low density regions because of X-Y CTE concerns.
I cannot superimpose the two partitions on N/S and F/S because of
'edgy' 28V switching on the output stage - they must stay apart for signal 
integrity. It is a 10-lyr. with lyrs 2 and 9 being 2oz. full coverage.