Mail*Link(r) SMTP FWD>DES: 1500V isolation
Dom: Posted an inquiry (full address follows immediately below) about the
effect of electrical transients -vs- electrical isolation (spacing). I'm
sending you this preliminary e-mail to let you (and others) know something is
coming (unless somebody else does it for us).
-------------
Regards, JNA Telecommunications
Limited
___ _____ 16 Smith Street
Dom Bragge (VK2YAK) __ / / |/ / _ | Chatswood NSW 2067
PWB Designer, (R&Ddiv) / // / / __ | AUSTRALIA
Tel: (+61 2) 9935 5792 \___/_/|_/_/ |_|
Fax: (+61 2) 417 3862 http://www.jna.com.au
---------------- Preliminary Response Follows -------------------
Date: 6/10/96 8:02 PM
From: [log in to unmask]
>Can anyone give me any idea as to how far apart I need to put tracks to get
>1500V transient isolation. These tracks are on the same layer. Using FR-4.
>The transients are 100 to 1000 uS.
I assume the transients you are designinging for (as stated,in the range of
100-1000 us (microseconds) are derrived from electrical switching transients,
as electrostatic induced transients (such as lightning) are generally much
faster and are in the range of 1-100 ns (nanoseconds). I unfortunately don't
immediately have available the information you need right now; however, I'll
get it together for you tonight and try to e-mail it to you tomorrow.
>Does duration actually matter?
Yes the pulse rate and duration are factors, the ionization time for a gas
(air) is a function of duration, rate, voltage and the type of gas.
>Is there a particular standard I should be looking at?
In the USA, there are a few standards that have transient requirements for
electrical/electronic products / components. For most alternating current
(ac) power source application, in the USA the design standard (I believe) is
something like 1200 Vac plus twice the applied voltage (rms) which equates for
most applications to a test voltage of about 1700 Vac (rms). I believe for
the IEC community, the requirements are for 2500 Vac (rms). Both of these are
a test at the specified voltage for a specified length of time, and are to
access/ealuate a product's ability to withstand a "transient" (as well as to
evaluate electrical leakage currents). If the equipment you are designing is
for interconnected to the electrical power system (from the "grid" of your
local power company) there are more sever (greater electrical spacing)
requirements depending on how clean/dirty the source of electrical power is.
Likewise, I'll try to get these for you.
>Are there any coatings one can apply to increase "breakdown strength" & hence
get the tracks closer?
IMO, do not use any conformal-like coating in place of "primary insulation" --
it's not -- it's too risky, and gives you a false sense of security.
Conformal coatings should only be used to control the "cleanliness" between
conductors of sufficient electrical spacing or when the physical design
conditions are such that the conformal coating (thickness) is being used as
the "primary" insulation.
Initial electrical breakdown between surface conductors do not occur in the
base material or directly on the surface of the base material; instead it
occurs a few mono-atomic layers above the surface of the base material,
normally in air according to the Paschen Law breakdown of gas law. That is
unless some other "more conductive residual krud" (or as a politer term -
"surface contamination") is on the surface of the base material between the
conductors. The following sketch is provide to illustrate how breakdown
occurs on conformally coated materials for both HVdc (High Voltage direct
current) and HVac.
eeeeeeeeeeeeee
++++++++++++ -------------e e+++++++++++++
cccccccccccc+ eeeeeeee -ccccccccccccccccccccccccccccccccccccccccccc
x+x+x+x+x+xcc+e e-ccx-x-x-x-x-x-xccccccccccccccccx+x+x+x+x+x+x
x+x+x+x+x+xccccccccccccccccx-x-x-x-x-x-xccccccccccccccccx+x+x+x+x+x+x
ddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd
ddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd
+ & - represents a charge that is transfered through the conformal coating (c)
c represents the conformal coating
x represents a conductor that has an applied + or - voltage to it
d represents the base material (dielectric)
e represents electrical breakdown path (in air) for coated conductors
The above figure illustrates two conditions, the left-half represents a
tradition "thin conformal coating" in that the coating (for the most part)
follows the contour of the conductors and tends to "fill in" the spaces
between conductors. the right-half is where a "thick conformal coating" is
applied in such a thickness as to "fill" the void between conductors and
essentially "level" the surface of the board.
For HVdc Applications-
For dc applications, an electrical charge is conducted through the conformal
coating (as a function of insulation resistance and time) charging the outer
surface of the coating to the applied potential. "Electrically" this surface
charge of electricity looks like one electrode of a capacitor (with the other
electrode being the printed boards conductive pattern). At some point in
time, the electrical stress some where on the angled surface between the "+"
surface charges over one conductor and the "-" surface charges on the other
conductor will exceed the Paschen minimum electrical breakdown voltage and
there will be an arc between the + and - charges until the voltage is reduced
below the de-ionization potential. The neat thing about this (;-) (my dry
sense of humor is showing), is that it keeps on repeating itself until
something else happens. Such as the repetitive discharges are a plasma-like
arc, and will eventually burn a hole(s) through the conformal coating, and the
plasma arc in air across the conformal coating radiates heat, and will
eventually "carbonize" the surface of the conformal coating leading to
catastropic failure of the product. Then everything is down-hill from there.
An example of this charge transfer is you VDT monitor for you computer or your
TV set. CAUTION, CAUTION, CAUTION,, the following is an example, DO NOT DO
IT. On some high voltage VDT's (or TV sets) when you back the back of you hand
or arm toward the viewing surface of a VDT monitor, you will feel the hair on
the back of your hand/arm start to "Tingle" from the high voltage charge that
has been transfered through the insulative glass to the viewing face of your
VDT. Using static volt meters, you can measure up to 35 kV (sometimes more)
on the face of a TV set. Under the right conditions, you will receive a
painful electrical shock when the surface of the VDT monitor discharges
through you -- so don't do it. To improve VDT safety, some VDT's have a
transparent conductive film over the face of the CRT to "bleed-off" to ground
the transfered electrical charges, and therefore lowers the probability of
shocking the user. Comment -- This charging of insulative surfaces is nothing
new, ESD control keeps a lot of companies and people in business and employed.
For HVac Applications-
HVac has some serious and subtle effects when using mixed dielectric constant
materials. From basic electricity/physics, the ac resistance of a capacitor
is called capacitive reactance and is usually represented by the symbol Xc,
and the Xc formula of a capacitor is Xc = 1 / (2 pi f C), where "f" is the
operating frequency in Hz, and C is the capacitance in Farads. Therefore, for
any given frequency, the Xc (ac resistance) of a capacitor is inversely
proportional to capacitance (the bigger the "C" the small the Xc). Now if we
have two capacitors in series, the greatest ac voltage will be across the
smallest capacitance. Remembering also, if we have a capacitor of a specified
area and uniform dielectric thickness, the capacitance is directly
proportional the the dielectric constant of the insulative material. For
example, a capacitor of a certain size (overlapping area and spacing) will
have a capacitance of "C" for an air dielectric, for most polymeric materials
their dielectric constant is about 3.5 so the same capacitor will have a
capacitance of 3.5 C, and if the dielectric is epoxy-glass (dk ~4.5) the
capacitor will have a capacitance of 4.5 C. Now what's this mean to HVac??
With two equal valued capacitors in series (area and dielectric thickness),
the Xc's at any frequency are equal and the ac voltage across each capacitor
is equal, as is shown in the left half of the following illustration. Where
the HVac is applied between surface/conductor #1 and #2. The "overlapping"
area of high voltage terminal #1 and #2 and the mid-surface areas are all
equal. The dielectric thickness of d1 and d2 are equal.
------ ++++++++++++++++++++ ------ ++++++++++++++++ HVac #1
| | d1d1d1d1d1d1d1d1d1d1 | | d1d1d1d1d1d1d1d1
| V/2 d1d1d1d1d1d1d1d1d1d1 | 0.8V d1d1d1d1d1d1d1d1 dielectric #1
| | d1d1d1d1d1d1d1d1d1d1 | | d1d1d1d1d1d1d1d1
V --- ssssssssssssssssssss V ---- ssssssssssssssss mid-surface
| | d2d2d2d2d2d2d2d2d2d2 | | d2d2d2d2d2d2d2d2
| V/2 d2d2d2d2d2d2d2d2d2d2 | 0.2V d2d2d2d2d2d2d2d2 dielectric #2
| | d2d2d2d2d2d2d2d2d2d2 | | d2d2d2d2d2d2d2d2
------ -------------------- ------- ---------------- HVac #2
When dielectric constant d1=d2 When dielectric constant d2=5*d1
Now lets take the d2 dielectric and change it to a material having a
dielectric constant of 5 (everything else - area, thickness and HVac being the
same). The capacitance of mid-surface -to- HVac #2 terminal now increases by
5X due to the increase in the dk of dielectric #2. With the application of
HVac, as shownin the right-half of the above illustration, the voltage between
the mid-surface and HVac terminal #2 is 20% of the applied voltage where as
the voltage between the mid-surface and HVac terminal #1 is now 80% of the
applied voltage.
What this mean - or the point? If you have a "marginal air" electrical
spacing between conductors, then with HVac the worst thing you might do is to
partially reduce the electrical spacing be adding an insulative coating to
partially fill the space thinking the coating thickness will "protect" my
circuit --- it may not, in fact it might increase the risk by reducing the
time to failure.
Dom's last concern---
>How 'bout for inner layers?
For inner layers, the dielectric should be "homogeneous" and therefore, the
electrical spacing depends on how much you want to "push" the dielectric
strength of the "weakest" material you are using. If your design includes
HVac (High Voltage alternating current) then the dielectric constants of your
insulative materials becomes very critical. This is because the portion of
the HVac will be proportionally greater across the dielectric with the lowest
dielectric constant (as discussed above).
Hope this will help to satisify your needs, I'll try to get the IOU's together
and send them tomorrow.
Ralph Hersey
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Subject: DES: 1500V isolation
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Date: Tue, 11 Jun 1996 11:35:26 +1000 (EST)
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