In message [log in to unmask] writes
>     1.) HOW DOES THE VENDOR COMPENSTATE FOR PLATING IN HOLES WHEN THE 
>     DESIGN IS UNBALANCED.  DESCRIBE THE CONSIDERATIONS IN A DESIGN TO 
>     ACCOMMOATE THIS SITUATION.  HOW CAN A DESIGNER COMPENSATE FOR THIS?  
>     DESCRIBE "INTERNAL PLATING THIEF'S", HOW AND WHEN THEY ARE USED.
>     
>     2. )DEFINE PROGRAMMING PROCEDURE FOR ELECTRICAL TEST.  DEFINE THE AOI 
>     PROCEDURE: (AUTOMATED OPTICAL INSPECTION)
>
I hope this is not too simplistic for your needs:-
1)
Unbalanced design for plating can be side to side eg ground plane one
side, tracks on the other. This can be compensated for in plating by
applying the correct current for each side with two separate rectifiers.
If this is not possible, then plating in the holes will be thinner
towards the ground plane or high copper side.

The other type of imbalance is where areas of high and low copper
density appear on the same side. This is more of a problem but can be
improved by adding cross-hatched copper areas of the same density as the
rest of the pattern to areas of bare laminate. If this is not possible
the large areas of copper should be placed around the outside of the
plating area with isolated fine track areas at the centre. The area of
high plating current density is around the outside edge of the plating
window. Plating thieves are used as a last resort adjacent to problem
areas but this should never be necessary with good design and good
plating methods.

The density of holes can also be a big factor and is often overlooked.
The area of hole wall significantly increases the copper area and if
there is an uneven distribution of holes this will affect the plating
distribution. For average board designs, it should be possible to
achieve a maximum variation of 0.5mil from the thickest plated hole to
the thinnest. Normal hole size tolerance is +/- 2 mils so this is not a
problem. With tight tolerance hole sizes, plating becomes more critical
so don't tighten up on the tolerance unless you have to.

Try to maintain a uniform and equal density of copper pattern on both
sides and avoid concentrating holes.

2)
The procedure for electrical test is to derive the fixture and test
programme from the Gerber data or netlist. The test programme is loaded
and the pwb's compared to it. It is not good practice to start with a
production panel to learn the interconnections as the batch may have a
common fault. Once a pcb has been produced correctly and verified, this
'golden board' may be used to learn from if necessary.

AOI is generally used as a tool for inner layer inspection prior to
multi-layer lamination. Many companies use AOI with great success but do
leave it to the fabricator to select the best method for testing each
product. I prefer 100% electrical test as this is more reliable and much
quicker, although two fixtures are needed for inner layers. AOI is
dependent on the human operators interpretation of spurious defects, of
which there can be many, and this can result in a high unreliability
factor due to the real defects being missed. (This is based on real
experience and also seeing one mass lam facility  install electrical
test in addition to their existing AOI machines.)
-- 
Paul Gould

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