Stephen,
The only time I have seen this problem was when the soldermask
om the board had undercut around pads.  The undercut trapped contaminates.
We defined the defect as typeI and typeII.
TypeI : This type of soldermask undercut leaves a small path under
        the mask to a feature such as a pad.
TypeII : This type of soldermask undercut leaves a large path to a feature.
The typeI is more serious in that it trapes more contaminates.
This pcb ran 10vdc @ 0.010' spacing and under humid conditions.  
We scrapped the boards.

---------------------------
John Laur (PCB Design)
Rockwell Automation
Allen-Bradley Co Inc.                 
1201 South Second Street
Milwaukee, WI 53204
+1 414 382 2162 (fax)
+1 414 382 2393 (phone)

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> From:  Stephen Ayotte
> \\\\\\\EM Quality Engineering
> \\\\\\\Bldg. 14-3 Col F5 5-1537
> Subject: PCB Build
> Does anyone have any experience with the spacing between
> PTH lands and a power plane on the external to avoid/prevent
> dendritic growth between the PTH and the power plane?
> 
> The power plane is going to have 48 volts of applied bias.
> The PTH could be ground or some other signal applied bias.
> 
> Thanks.
> 
> **** IBM MD Product Quality Engineer****
> ****         OEM Quality Engineer   ****
> 
>