Just a bit more info on this subject from one of our engineers here at the 
EMPF:
"Some guys at ITRI are doing work in this area. Marshall Andrews (512) 338 
3702 would have more info."
 --------------------------------------------

                As Joe stated, those individuals that are developing the
        techniques to successfully produce these micro/miniature packages,
        are being driven because the chip/die technology has far surpassed
        the capabilities of the standard PCB I/O. The initial vehicles to
        approach adapting >800 (even >1200) I/O per inch to standard PCB
        is in the format of a high density interposer or DCA (adapter type)
        carrier.(There are others methods also) Some of these carriers
        have the ability to dissipate high heat due to special techniques
        or metals utilized.
                I believe that at some point in time the miniature
        footprints may be found on standard PCB surfaces.
        Approaching success on that surfaces will entail resolving
        extremely high density techniques. (ie, .002/.002, pad in via, or
        via in pad, BV (or equivalent)...etc. just to name a few) Joe has
        mentioned many of the fun "rude awakenings" that you may encounter.
        Mike, there is people dabbling in this arena. I believe some samples
        will be on display at Nepcon. It's good to hear from you again.
        Hope to see ya puttin' in yer 2 cents along wit ta rest of us.

         ^   ^
      Gr O   O vy
           V
         \___/

______________________________ Reply Separator
_________________________________
Subject: Re: Small Via Formation
Author:  [log in to unmask] at SMTPLINK-HADCO
Date:    1/23/96 9:19 AM


Very good questions asked by Michael regarding the future of small vias in
PCBs. This is a very important subject. One key driver is the entrance and
rapid evolution of Chip Scale Packaging (CSP)  These new minimalist packages 

will require such small vias (and also finer lines). The interesting thing
about these new package formats is that they will probably be, at once, both 

the highest performance and the least expensive packages for ICs. Projecting 

the impact of the packaging to the PCB, it is clear that they will probably
be more expensive per unit area but less area will be required for
interconnection. Key to enjoying those higher profits is good process
control.
Excepting the need for leasehold improvemnts such as clean rooms, it is
reasonable to argue that it costs no more to produce a one or two mil line
than it does to create a ten or twenty mil line. The materials avialible
today are clearly process capable as evidenced by those among us who produce 
such
products daily. The net effect of the finer lines and smaller holes should 
be
that the boards will be less costly, per function, to the OEM and thus to 
the
end user. What will have to be tossed out are the tired and dated concepts 
of
fixed costs per unit area and the deeply entrenched "buyers mentality" which 

we, as an industry, seem to collectively nurture. There will be need for a
concerted effort at re-education to transform buyers into "technology
procurement specialists" who truly understand the dynamics of these changes.
A continuing dialog on this subject, "to argue it out",  is invited and
encouraged...

Cheers,
J. Fjelstad