At 08:39 AM 9/16/2009, Robert Kondner wrote:
>Hah?
>
> The wavelength of 800Mhz is 1.2 feet. So y/20 = .72 inches. Even the
>higher harmonics are over 100 mil.
a little cell phone industry humor there. 800 MHz. Get it? ;^)
> The length of a via to an internal plane is about 20 mils? The is 1/5 of
>the higher harmonics. Give me a break.
>
> You must be joking if you think placing a "Swiss Cheese" plane on the PCB
>top for saving a 10mil via distance is going to affect signal impendence.
>That "Swiss Cheese" plane is probably a greater Z than the vias. Still
>compared to a wavelength of 1.2 feet it is not going to be measureable.
Benefit is not so much for impedance as it is for distributed
capacitance if designed to take advantage of it. Mute point in our
world anyway. Except for emulator cards almost all of our work is on
high I/O.4mm and .5mm pitch devices (670-1000 pins). Forget swiss
cheese. There's nothing but fanout and hookup going on in those 6 or
9 mil routing channnels.
>Bob Kondner
>
>
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Dwight Mattix
>Sent: Wednesday, September 16, 2009 11:27 AM
>To: [log in to unmask]
>Subject: Re: [TN] Ground Pour Under BGA
>
>At 07:36 AM 9/16/2009, Lee Hill wrote:
> >Ok Bob I will try to find it.
> >Yes, the problem assumes "high frequency". F>100 MHz would be high enough.
> >And for today's technology that is pretty "low" :-)
>
>Hah. These days DC is about 800 MHz. /heh
>
> >Traditional lumped-element noise theory models capacitive coupling as
> >"small" value of capacitance. In other words, it is "accidental", "stray",
> >or "parasitic". If it were a big value it would be obvious to the designer
> >and he/she would avoid it at all costs. The Z of the stray capacitance at
> >the noise frequency determines the amount of noise current injected. The
> >impedance of the victim circuit determines the noise voltage that is
> >developed. You mention the impedance of vias, I'm not sure what they are
> >but I don't think they are relevant to the E-field coupling from the body
>of
> >the noisy IC to say, a nearby enclosure cover, or a wire attached to the
>PCB
> >a few cm away, or to data transceiver IC a few cm away.
> >
> >Tiny amounts of mutual inductance (picoH) and capacitance (pF) do cause
>many
> >noise problems. The case I was referring to above is not "electrostatic
> >coupling", "static" implies stationary and/or "DC".
> >
> >Best Regards
> >
> >Lee
> >
> >-----Original Message-----
> >From: Robert Kondner [mailto:[log in to unmask]]
> >Sent: Wednesday, September 16, 2009 10:21 AM
> >To: 'TechNet E-Mail Forum'; 'Lee Hill'
> >Subject: RE: [TN] Ground Pour Under BGA
> >
> >Lee,
> >
> > If you still have any links to that research I would love to read it.
> >
> > Ok, I can see a electrostatic (Near Field) effect is possible, I recall
>my
> >Hog Wash label from that effect. But as far as the chip body to board
> >capacitance it would have to be a pretty high frequency to be less than the
> >Z of a couple 10 mil long vias. At least I think.
> >
> > Thanks again, it is definitely something to think about.
> >
> >Bob Kondner
> >
> >
> >-----Original Message-----
> >From: TechNet [mailto:[log in to unmask]] On Behalf Of Lee Hill
> >Sent: Wednesday, September 16, 2009 10:10 AM
> >To: [log in to unmask]
> >Subject: Re: [TN] Ground Pour Under BGA
> >
> >There was good EMC research done about 5-7 years ago at the University of
> >Missouri-Rolla (UMR - now Missouri University of Science and Technology)
> >that investigated this design technique and explained how, why, and when it
> >might be helpful. I know it is tempting sometimes to dismiss seemingly
> >weird or useless PCB EMC design techniques out-of-hand, but there are a lot
> >of smart people around the world spending a lot of time doing mathematical,
> >computational, and experimental research work to analyze, understand, and
> >prove the usefulness or uselessness of many different aspects of PCB
>design.
> >
> >For this specific example, the basic idea is to encourage capacitive
> >coupling from the top of the IC back down to the "low side of the source",
> >which in general is the "ground plane" of the PCB. For it to be perceived
> >as effective, many conditions must be met 1) the IC must be troublesome
> >source of E field coupling, 2a) there must be a "victim" of the E field
> >coupling, and 2b) the victim is sensitive enough or the regulatory
>emissions
> >limit low enough that the noise coupling is troublesome. "plane impedance"
> >is a little vague, it is not clear whether this refers to power bus
> >impedance (then there must be a second power conductor somewhere), or just
> >the impedance of the ground plane(s) alone, which is not defined without
> >first defining a complete signal or noise loop geometry. If we have a PCB
> >where there already is a "ground" plane at layer 2, then there probably is
> >not as much benefit to the technique for noise control. I think the
>research
> >was spurred by the use of 4 or 6 layer boards, where the IC might not
> >"normally" have a "ground" plane directly beneath it.
> >
> >Best Regards
> >
> >Lee UMR '92
> >
> >Lee Hill
> >
> >SILENT
> >10 Northern Boulevard, Suite 1
> >Amherst, NH 03031
> >USA
> >+1 (603) 578-1842 (v)
> >+1 (603) 578-1843 (f)
> >+1 (508) 341-3947 (m)
> >[log in to unmask]
> >
> >Electromagnetic Compatibility and RF Design, Troubleshooting and Training
> >
> >
> >
> >
> >-----Original Message-----
> >From: TechNet [mailto:[log in to unmask]] On Behalf Of Robert Kondner
> >Sent: Wednesday, September 16, 2009 8:42 AM
> >To: [log in to unmask]
> >Subject: Re: [TN] Ground Pour Under BGA
> >
> >Hi,
> >
> > What would be the goal of placing atop side GND plane under the BGA?
> >
> > Low Z Gnd return? Electrostatic shield?
> >
> > Having a plane under the BGA vs another layer is not going to make a
> >difference in plane Z.
> >
> > Sounds like a good chance of creating shorts if the solder mask chips or
>is
> >damaged during rework.
> >
> >Bob Kondner
> >
> >-----Original Message-----
> >From: TechNet [mailto:[log in to unmask]] On Behalf Of Guy Ramsey
> >Sent: Wednesday, September 16, 2009 7:43 AM
> >To: [log in to unmask]
> >Subject: Re: [TN] Ground Pour Under BGA
> >
> >IPC 7095, BGA Technology by Lau.
> >
> >-----Original Message-----
> >From: TechNet [mailto:[log in to unmask]] On Behalf Of Toby Carrier
> >Sent: Tuesday, September 15, 2009 8:45 PM
> >To: [log in to unmask]
> >Subject: [TN] Ground Pour Under BGA
> >
> >Hello all,
> >
> >Is it a good idea to create a top layer ground flood under a BGA package? I
> >am
> >guessing that the fanout will not allow much area for the ground pour, am I
> >correct in thinking so? Does anyone have any good reference info on this
> >topic?
> >
> >Also, if you don't have a ground pour under the BGA, how will that affect
> >the
> >impedance control of the traces going to the BGA ball?
> >
> >Thanks for the help,
> >
> >Toby
> >
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