With regards to the concern listed below, final product requirements usually
stipulate a minimum dielectric spacing to ensure that two isolated nets are
not unintentionally shorted together.  This also permits a higher level of
long term reliability with regards to circuit integrity. 

In order to accomplish this, plated through holes present on the same plane
as  internal conductors should allow for the total material movement and
tolerances such that, in the worst case, the minimum dielectric is
maintained. Non functional pads accomplish this since the design of these
pads should allow for the total worst case cumulative error (dimensional
stability of laminate, drill inaccuracy, artwork error, etc.) such that
holes contained within the non functional pads will always maintain minimum
spacing. This pad forces designs to allow for conductor-to-pad spacing that
will be no worse than the minimum dielectric by default.

When non-functional pads are removed however, designers often ignore the
space that was previously occupied by these pads and rout circuits close to
the holes with little or no regard for actual spacing on the final product.
In the purely defined CAD data, the spacing that exists on the database
appears to be sufficient however, the cumulative error during pwb
manufacturing is not considered. This is a problem.

In your example you stated >0.010 inch clearance. In this case, should this
condition exist between the edge of plated hole (with no pad) and the
nearest circuit, there are some questions that arise :

1) Is the hole size considered the finished hole size or tha actual drill
diameter used by your board supplier ? (Drill hole sizes can be up to 0.006
inch LARGER than the final size to allow for plating and solder levelling)

2) What is you minimum product specification for dielectric spacing? (this
is typically 0.005 inch or less, based upon application)


When you consider the above 2 points, in your example if 0.011 inch
clearance is designed in this case, then the actual allowance for total
manufacturing error would be :

    0.011 - (0.003 + 0.005) = 0.003
      ^        ^        ^       ^
      |        |        |       |
      |        |        |        \ 
      |        |         \        total remaining tolerance allowance 
      |         \          minimum dielectric
       \         drill hole increase radius
         total space by design


Needless to say that 0.003 inch is not sufficient for total manufacturing
tolerances during pwb manufacturing.


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------------------- reply separator  ---------------------------
>
>Relating to one of the last posting on 'Non-Functional Pads'.
>
>Are PCB designers and/or PCB fabricators specifying minimum drilled hole to 
>internal feature spacing?
>Example:  The space from a drilled hole to the nearest internal pad or trace 
>not on the same electrical net.  I am not including the connection pad or 
>the non-functional pad that may be present on the same layer as the feature. 
>  We currently currently try to keep this spacing above 10 mils.
D. Rooke
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