Mail*Link(r) SMTP FWD>DES:FAB:ASSY: Breakdown
Dom,
I agree with all of the comments you've received thus far, this is another one
that is basically "don't do it".
As mentioned by both Jerry Cupples and Bob Holmes, the design is in a high
risk situation. Adding to Bob's comments, the solder resist over the high
voltage conductive patterns is not sufficient dielectric thickness. Assume,
as Bob mentioned, the surface of the PB becomes coated with dust, dirt, salts,
etc. and absorbed humidity, these contaminants can become very conductive,
assume worst case a conductor. The design has 305 micrometer electrical
spacing between conductors; but from the surface of each of the conductors,
through the solder resist dielectric, to the conductive layer of contaminants,
the dielectric thickness will be in the range of 13-50 micrometers for each
conductor. Now your effective dielectric thickness between conductors is
25-100 micrometers, which with 1500V is kind of pushing the dielectric
strength of the material, not including coating anomalies (such as mentioned
by Bod as bubbles, thin spots, etc.).
As Jerry commented, the implied, the interface where the solder resist meets
the surface of the printed board is the most critical, and has got to be a
"near perfect" bond, under all environmental and use conditions, it can't
seperate -- otherwise it's arc-over time.
IMO, in concert with the other comments, don't do it, or make sure you've got
good insurance coverage.
In our work, we use as a "rule of thumb" 400 Vdc (or peak ac) per mm (or 1
inch per 10 kV) as our surface electrical spacing standard for many years with
essentially no problems. (Yes it's conservative, it's about 15% of the
breakdown of air at STP). And yes, we use this electrical spacing for any
conductors that are conformally coated. When you get into serious high
voltage application, you need to "burry" all high voltage in a "homogeneous"
dielectric that will meet all you electrical spacing requirements in all
directions and to any surface that will/can establish the greatest electrical
gradients (stress).
Ralph Hersey
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--------------------------------------
Date: 8/6/96 6:14 PM
From: [log in to unmask]
Using 1.6mm FR4 with LPISM, we need information on how to prevent
breakdown between tracks on the outside layer separated by 12thou,
when subjected to 1500V continuously. What sort of coatings/processes
aid this?
--
Regards, (A4fonHPUX9.0onHP715,710) JNA Telecommunications
Limited
___ _____ 16 Smith Street
Dom Bragge (VK2YAK) __ / / |/ / _ | Chatswood NSW 2067
PWB Designer, (R&Ddiv) / // / / __ | AUSTRALIA
Tel: (+61 2) 9935 5792 \___/_/|_/_/ |_| email [log in to unmask]
Fax: (+61 2) 9417 3862 http://www.jna.com.au
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Dom Bragge asked:
>Using 1.6mm FR4 with LPISM, we need information on how to prevent
>breakdown between tracks on the outside layer separated by 12thou,
>when subjected to 1500V continuously. What sort of coatings/processes
>aid this?
I'd sure want a big fire extinguisher handy!
You'd want the board scrupulously cleaned, then have something like
Parylene conformal coating applied post assembly - something thicker and
with a higher dielectric than a normal solder mask. Thin coatings like SM
are not really occlusive enough to prevent moisture penetration in even
fairly benign environments. That's a bunch of EMF and a pretty small gap.
You must be talking about a tiny current?
You could consider using a laminate other than FR-4, again - the best
possible dielectric rating. FR4 works real nice at about 5 V.
(warning, the above opinion might be disclaimed instantly, and can only be
offered in a highly secret environment like TechNet)
Let's hope you get a better suggestion...
73,
Jerry Cupples
KC5SXA
From: [log in to unmask] (Jerry Cupples)
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Dom Bragge asked a question on high voltage design rules: 12 mil space 1500 V
First the caveats: The voltage you quote is definitely in the "marginal" area.
I believe that it violate IEC guidelines. I would be less concerned if the
voltage represented a fault condition or was applied for a short time. A
continuous application of 1500 V is very risky.
That said, let me address your question. There are at least four possible
failure modes. Ranked in order of risk they are the following: dust buildup,
surface flash-over, dielectric failure, and air breakdown. Let me comment on
the risk from each of these
Dust build up is the most serious problem. I assume the voltage is DC (if it
is AC there are other problems). The fields associated with a DC voltage
attract dust. (Think of the high voltage supply in a TV set). Over time the
dust will build up and span conductors. Under high humidity conditions, dust
absorbs moisture and creates a leakage path that can carbonize leading to
failure. We have seen this failure under field conditions. The only solution
is to this is to maximize the separation of uncoated features and to assure
there are absolutely no pinholes in the soldermask. Pinholes are the real
risk so a double soldermask coating should be used. A conformal coating of the
assembled board would also be a good idea.
Surface flash-over is the second serious risk. Any dielectric surface
provides a breakdown path for high voltage. The breakdown follows the
surface, so a smooth surface is riskier than a rough surface (Think of the
shape of the insulators they use on high voltage transmission lines).
Unfortunately soldermask is very smooth and 1500 volts can arc across gaps
up to 30 mils wide. This phenomena is initiated at any "triple point" where
air, dielectric and metal meet. The solution is to assure that the conductor
is totally encapsulated. Any soldermask pinhole is a source of an arc that
will flash to the nearest uncoated land. Therefore you must assure pinhole
free soldermask.
I have little information on the long term reliability of either FR-4 or
soldermask under high voltage conditions. Voltage is an acceleration factor
in dielectric failure, but my sense is that most modern materials provide
margin and 1200 volts is not a problem. I have seen application where
standing voltages of 300 to 500 volts gave no long term problem. I would be
willing to gamble that you could get away with 1500 volts. However there is a
risk of long term dielectric failure, particularly if the temperature or
humidity is high.
Air breakdown should not be a problem. The Paschen curve says that the maximum
spark gap for 1500 volts is about 8.5 mils. If you assure a 12 mil space air
gap breakdown will not be an issue.
To summarize. The two biggest issues with 1500 V are dust buildup and surface
flash-over. The solution to both problems is to absolutely exclude soldermask
pinholes. (The electric field easily finds even the most minute hole on a line
edge). If you can exclude pinholes and guarantee a 12 mil space I think you
may a reasonable shot at a good system life.
Good Luck
Bob Holmes
Lucent Technologies
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