Take a look at the board stack-up. If you have dielectric spacings between
layers of 8 mils or somewhere near 8 mils, it might have been built using a
single ply of 7628 prepreg (to keep cost down), this is not a good practice.
Separation between innerlayers or broken vias can be a risk.
thanks,

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Dwight Mattix
Sent: Wednesday, September 19, 2012 11:55 AM
To: [log in to unmask]
Subject: Re: [TN] Broken Vias


That is a (most) robust combination. The San Ei is the benchmark for
via fill reliability in our applications and experience. We have
several applications that it is the _only_ via fill to pass our
reliability demonstration. Use it in combination with several
materials: most commonly FR370HR or an equivalent.


At 05:37 PM 9/18/2012, Robert Kondner wrote:
>Hi,
>
>
>
>This is a follow up on the broken vias on a board with plugged and plated
>through vias.
>
>
>
>The laminate is 370HR (Tg 180) and the fill material is  PHP-900 IR-6P from
>San-Ei Kagaku (Tg 168).
>
>
>
>I do not have cross section pictures yet.
>
>
>
>If anyone has any ideas on how these material might react to a lead free
>reflow process and via barrels would be broken please let me know. I am
>interested in any and all ideas.
>
>
>
>Bob K.
>
>
>
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