Here is an earlier email trail.....
-------- Original Message --------
Subject: Re: [TN] Via in (SMT) pad
Date: Wed, 18 May 2005 11:09:44 -0400
From: Dave Seymour <[log in to unmask]>
Reply-To: TechNet E-Mail Forum <[log in to unmask]>, Dave Seymour
<[log in to unmask]>
To: [log in to unmask]
References: <[log in to unmask]>
Here is a fabrication note I worked up with the fab shop.
"All vias drilled equal to or less than .0xx shall be plated, then
filled with non conductive material, such as Peter's paste # SD-2361,
or equivalent. Surface to be planar prior to final plating and
metallization.
Boards must be suitable for via in pad technology."
http://www.peters.de/
I would recommend working with your fabricators to find the best solution
to your requirement. Without mentioning names, Most large fab houses can
handle
this either internally or through subcontractors.
.028 is pretty big these days to fill. (?)
Most prefer to flood the entire board, rather than be selective.
Hope this helps,
Dave
Allen T. Maddox wrote:
>We have a couple engineers who are insisting on using Via in (SMT) pad. I'm not talking about micro via in a BGA pad. I'm talking about vias with a 10 to 28 mil hole in a 0805, PLCC, QFP, and other SMT pad.
>In order for this to work in manufacturing they must be filled, without voids, and capped flush on the solder surface.
>Does anyone know of a board house that does this process?
>
>Would you have an idea what the general cost effect to a board for this process and does it make a difference if it's one via or 500 vias? Cost difference between electrically conductive and thermally conductive fill?
>
>Any information would be helpful,
>
>
>Allen Maddox C.I.D.
>Sr. PC Board Designer
>GAI-Tronics, Corp
>610-796-5854
>PO Box 1060
>Reading, PA 19607-1060
>
>[log in to unmask]
>www.gai-tronics.com
>
>
>
--
Dave Seymour, CID+
Catapult Communications Inc.
800 Perimeter Park Dr, Suite A
Morrisville, NC 27560
Direct: (919)653-4249
Main: (919)653-4180
Fax: (919)653-4297
[log in to unmask]
Carl VanWormer wrote:
>I am looking for guidance on using vias in pads of surface mount
>components. The concept is great for high speed design, since it gives
>the least inductance for mounting bypass caps. It sounds easy, but I'm
>sure there are some pitfalls and there may be some rules I will break.
>Any guidance towards documents on this combination would be appreciated.
>Also, any stories to scare me away from this approach will be fun to
>hear.
>
>Later,
>Carl
>
>
>
>
>
>Carl Van Wormer
>Cipher Systems
>1800 NW 169th Place, Suite B-100
>Beaverton, OR 97006
>Phone (503)-617-7447 extension 20
>
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>
--
Dave Seymour, CID+
Catapult Communications Inc.
800 Perimeter Park Dr, Suite A
Morrisville, NC 27560
Direct: (919)653-4249
Main: (919)653-4180
Fax: (919)653-4297
[log in to unmask]
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