Mail*Link(r) SMTP               FWD>Open vias problem

Mark Lettang, <[log in to unmask]> expressed a concern about some small
diameter plugged and un-plugged plated-through hole (PTH) via problems in a
small percentage of some printed boards.

Questions were raised about plated shut vias, and electrical test data.  Most
of his questions have been addressed by previous responses.  The following are
some additional concerns / considerations.

Mark

Trapped residual plating solutions in the PTHs has been mentioned, another
concern though would be trapped etchant.

You could have a (gross??) latent failure problem.  For example, with almost
plated closed holes, you probably have some variation in plating thickness
"dog bone" through the holes, between holes in the same board, and board to
board.  This combined combined with trapped reactive plating/etching chemicals
will etch-through the weakest link (via) first, then the next weakest, and so
on, and so on.  Therefore, even you "good" boards should still be suspect.

IMO you've got to do some failure analysis to get a better handle on the
problem and to identify if there is a unique or random pattern to your
existing failures.  For example, you may observe all (most) failures have
occured in a "high current density" area of conductive patterns, where the PTH
hole plating is severely dog-boned due to throwing power of the plating bath
and dog-boning is enhanced by the reduction in the hole diameter at the lands.

It could be your E-test is ok, you've just got a "chemical reaction
time-related" latent failure problem.  (Still not a desirable situation)

Ralph Hersey
e-mail:  [log in to unmask]