Also, I would actually measure and verify the thickness of the 5 mil
stencil if the process is that critical. The typical range is 5.5-5.6
just as Andy stated, but oftentimes I have seen stencils have specific
areas as low as 3.5 mils while the other areas were 5 or 5.3 mils, which
is worse in my opinion, as it will skew your Cpk well to the left.
No, banish that idea that just popped up in your head of adding Kapton
to the thin areas of the foil, as the kapton tape simply prevents full
gasketing of the stencil to the board and causes excess paste, squeezout
and smears in the apertures immediately around where it is applied. 
It is better to insist that the stencil be correct and get a new one if
necessary, rather than attempt to "fix" oversize or undesired apertures
with tape.
However, what does work is to wash the stencil very clean and wipe with
IPA. Then place the stencil on a very flat surface with Kapton tape on
the bottom side of all unwanted apertures, carefully fill the unwanted
apertures with Loctite 3621, apply Kapton tape over the top side to trap
the epoxy, and cure in an oven. Then when you peel away the tape the
unwanted apertures are plugged, flat, and the Loctite sticks like crazy.
Caveat #1; it is very difficult to remove the Loctite completely should
you ever want those apertures back. Caveat #2, on some stencils the
bonding epoxy around the foil perimeter can be affected by the curing
temperature of 150 C for 10 minutes normally used for Loctite 3621. You
may wish to cure at 120 C for 15-20 minutes and keep a close eye on it,
which I have found works better.

Don't attempt to use a heat gun or any other concentration of heat in
one spot on the stencil to cure the epoxy, or it will warp and you will
end up with Sick Sigma printing results.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Andy Ng
Sent: Tuesday, December 02, 2008 1:07 PM
To: [log in to unmask]
Subject: Re: [TN] What are the industrial standards for Solder paste
printing limits?

Hi Rudolph,

Yes that's what I'm trying to say. A Cpk of 1.66 is actually 5 sigma,
which if measured for Cp is actually 10 std deviations, since you're
measuring for both LSL and USL. If your customer wants to have a
6-sigma, for a Cp calculation it will need to measure across 12 std
deviations. For Cpk, you need to find the minimum of either the lower or
the upper limits, in the solder paste printing height, will be the
upper.

As Richard mentioned, applying a kapton tape to mask off no-loads would
add to the thickness. There are also other factors, such as if your foil
is filmsy, ie. not fully stretched, or if you're using a carrier for
your PCB, or even if the stencil height is not properly adjusted, ie.
too close to the PCB, causing the stencil to "bow", hence a larger gap
in the center of the PCB than the edges.

In all cases, the paste deposit will be thicker than the thickness of
the foil. However, an average of additional 1 mil might be too large.  
Our vendor has an average of about 5.5 - 5.6  mils for a 5-mil foil to
account for these factors. This is probably why it is hard to get the
Cpk to 1.66, since your mean is not exactly the midpoint of your USL and
LSL, which is 5 mils. The constant "K" is calculated to offset the
difference between your midpoint (5 mils) and your mean (6 mils) to
derive to a lower Cpk.

Hope this helps.

Andy

Quoting Rudolph yu <[log in to unmask]>:

> Andy:
>
> Check out the website. Actually Cpk 1.66 = 5 sigma, cpk 1.33 is =  4  
> sigma. One will need a cpk of 2 in order to get to the 6 sigma region.
> The averge is about .15mm which is around 6 mil.  This is another   
> thing that our process engineer cannot answer me directly why the   
> solder paste dispoisition is 1 mil more than the the stencil   
> thickness on average? Any help?
>
> http://www.isixsigma.com/library/content/sigma_cpk_conversion_table.as
> p
>
> I dont know what the sample size the software is using. I am still   
> waiting for the answer from the SPI manufactuer.
>

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