RE>>Thermal shock of blind and buried vias   2/20/96

The engineer from the Digital/Kanata (Ontario) plant who developed this technique (Bill Birch) has an impressive database which shows the effectiveness of this technique.  It is much quicker than traditional thermal cycling tests.  If I remember correctly, you have to be careful with the design of your via array to ensure adequate and uniform heating.

Good luck,
Greg Bartlett
Mercury Computer Systems
Chelmsford, MA
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Text of message:
At Circo Craft we use IST to establish reliability performance of bare
printed wiring boards. This method employs an automated computer controlled
application of current which causes the substrate temperature to rise. By
cycling the test vehicle through a thermal profile, an assessment of 
reliability (time or cycles to failure) can be determined. 
Correlation between this method and traditional thermal cycle analysis
has been established. We have performed analysis on blind via substrates and
would be happy to discuss this issue further with you. 

D. Rooke
E-mail  : [log in to unmask]
Phone   : 514-694-8400
FAX     : 514-694-2696

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>
>We would need information and acceptance criteria on thermal shock testing 
>of blind and buried vias.
>The idea is to design the vias to form chain patterns and measure their 
>resistance/resistance change during thermal shock.
>Does anyone have experience on this or know of any standard test 
>pattern/method/conditions/ acceptance criteria?
>Your help is highly appreciated.
>Please, respond as soon as possible to IPC TechNet or directly to:
>          Liisa Mustala
>          Nokia Telecommunications
>          e-mail: [log in to unmask]
>
>
>
D. Rooke
([log in to unmask])