There are no-clean paste formulas that are pin probe friendly. 

Caps are a problem because they take time to stabilize. If you try to
measure too quickly the results are unpredictable.

Also, some types will read differently after a second application of DC, new
electrolytic caps for example. 

Also, our old friend the cracked ceramic will drive you nuts at ICT.

BTW, 99% is a very high first pass ICT yield. When I was writing tests for
another company we were happy with 80% coverage and 95% first pass yield on
complex boards. We rarely had false pass, less than 1%. False fail was hard
to measure.  


 
-----Original Message-----
From: Rojas, Juan [mailto:[log in to unmask]]
Sent: Tuesday, May 01, 2007 1:06 PM
To: TechNet E-Mail Forum; John Burke
Subject: RE: [TN] LeadFree - ICT FPY Benchmarking

Thanks John,

Yes we are having what it appears to be typical contact problems (due to
residues like: flux, oxidation, etc.) But I can not prove this yet; even
when we re-test a failing board it passes without doing anything to it; this
is not sufficient to convince my fellow process engineer.
We also have a lot of problems with capacitor tests that fails marginally it
is a very unstable test (caps)I attribute it still to residue but again it
is very difficult to me to prove it.

Any ideas? Comments are welcome.

Best regards,
Juan Rojas | Sr. Test Engineer

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