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Subject:
PCB Build
From:
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Date:
Mon, 22 Apr 96 16:25:31 EDT
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From:  Stephen Ayotte
\\\\\\\EM Quality Engineering
\\\\\\\Bldg. 14-3 Col F5 5-1537
Subject: PCB Build
Does anyone have any experience with the spacing between
PTH lands and a power plane on the external to avoid/prevent
dendritic growth between the PTH and the power plane?

The power plane is going to have 48 volts of applied bias.
The PTH could be ground or some other signal applied bias.

Thanks.

**** IBM MD Product Quality Engineer****
****         OEM Quality Engineer   ****

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