I agree with you guys that there is definitely nothing wrong with scoring at
all. Here are some insights I have on this subject.
* The V-grooves can be placed as close to the edge as possible, as long as
the grooves don't interfere with the copper image. (0.05" between boards is
mostly preferred)
* Usually, the absolute minimum clearance was determined by the thickness of
the board and the score web required.
Here is the equation: (Assume 60 degree Max. V-groove)
Absolute minimum required between boards =1.732 x (board thickness-web
thickness) + (0.02"<= adjustable safety factor)
F.Y.I. Typical web thickness 0.015" +/- 0.004 for 0.062" thick board
* For over-hang SMT or PTH components, pre-route at those locations can be
done to prevent interference.
* In my opinion, solder joint cracking should not occur if the right tools
and extra precaution are used in the depanelization process.
Thanks,
Michael Yuen
[log in to unmask]
----------
From: TechNet-request
To: TechNet
Subject: DES/FAB/ASSY: Part & via to board edge spacing
Date: Friday, April 26, 1996 11:44AM
The message below highlighted a general problem I have run into on
numerous designs. We constantly are trying to make the tradeoff
regarding whether to punch, route, or V-Groove a board. Each of these
techniques disrupt the board edge differently during PCB fab and also
when the part is broken out of the panel. One question that always
comes up is how close can we put parts & vias to the board edge.
In high density designs we are always trying to push this to the
limit, but I haven't found any general guidelines other that perhaps
keep features at least one board thickness from the board edge. The
concern is that either the FAB process will disrupt features and
things such as plated through holes, and the assembly depanelization
process will crack solderjoints as the board is flexed.
Do any Industry design rules exist for how close the following
features can be put to different types of board edges:
I'd love to have the following design rule table:
SMT parts TH Parts PTH Vias
Routed Edge
Punched edge
V-Grooved Edge
I have never seen IPC specs that delineate between type of edge, but
then I'm not well read.
Thanks,
[log in to unmask]
______________________________ Reply Separator
_________________________________
Subject: Re[2]: ASSY: Depanelization of SMT Board Assys
Author: [log in to unmask] at Dell_UNIX
Date: 4/25/96 8:42 PM
There is nothing wrong with scoring and a proper panelization and
scoring/routing can result in major PWB cost savings.
You just have to determine in advance how the boards will be
depanalized in production and design in the required criteria at the
PWB level up front.
If production plans on using equipment to depanel (punch, V-blade,
etc.), then you need to know the component placement keep outs
required around the edges of the board to clear the blades as well as
component height restriction,etc.
If boards are broken by hand, then DO NOT place any component close to
the edge since solder joints will get damaged. As Gary has indicated
below, the board dimension is not appropriate for breaking by hand and
I don't even know if there is enough room on the board (1/2" X 10") to
move components away from the edges for a punch equipment.
[log in to unmask]
Leo,
There are equipment out there (Pizza cutter!!) designed to depanel V-grooved
board. The V-blade used in those equipment will minimize bending stress
inflicted on the PCB to minimum.
(BTW,try to reduce the groove web to 0.015" if possible)
Yuen
----------
From: TechNet-request
To: Leo Reynolds
Cc: Technet
Subject: Re: ASSY: Depanelization of SMT Board Assys
Date: Thursday, April 25, 1996 8:37AM
Leo;
We experienced similar problems with a board the same dimensions. When we
investigated the excising methodology we were astonished to find that the
customer was attempting to break the boards away, by hand! Boards with
unsual aspect ratios, must be broken ustilizing a fixture that applys
uniform pressure at the break point. This should reduce the forces that get
transmitted into the board and the componet solder joints.
Regards,
Gary Ferrari
Tech Circuits
At 04:33 PM 4/24/96 -0500, Leo Reynolds wrote:
>We are a contract manufacturer and are currently having trouble with a 1
>1/2" X 10" SMT board assy. It was designed in a panel of 6, scored for
>eventual break apart and the original scoring left .018" of material in the
>groove. When we started to break them apart we found we were cracking some
>of the SMT caps. We've since instructed the PCB mfgr to go to a more
>standard .012" per one engineers recmmendation, but don't have samples yet
>to try. One of our process engineers attending Nepcon had several
engineers
>tell him that SMT boards shouldn't be scored at all.
>
>We are trying to determine the best course of action to recommend to our
>customer. The customers design engineer felt we shouldn't have had a
>problem with the original .018" groove so we may have to put together a
very
>god case for changing to routing or anyuthing else.
>
>Anyone have any recommendations?
>
>Thanks in advance for your consideration.
>
>Leo Reynolds
>
>
|
