Hello All

We too have experienced this conundrum for many years. We have been
marginally successful in avoiding it 
by:

1) For products that include SMT and wave solder (last process
performed), leaving the vias "open" (thus filled by wave) has worked
well. However, not all products have these characteristics.

2) Employing mechanical overclamped fixturing has worked well. The extra
fixture cost is amortized over volume through lower circuit cost (no
extra $$ for plugging). However, high IO BGAs cause a tremendous
concentration of localized test points which we know will overstress the
BGA joints during test using clamps to oppose the pin forces (i.e. the
module bends too much).

3) We employ plugging vias the same way others have. This process can be
costly and is not a technically robust process as others have noted. The
only items we've seen with it other than what has already been mentioned
are:

	Plugged vias unavoidably yield raised bumps (some as high as 2 mils)
which interfere with stencil 	printing fine pitch parts (by creating
localized non-planarity of stencil surface). Eventually paste winds 	up
on the bottom of the stencil and gets transferred to subsequent
production.

	When vias are placed under SMT devices, we have seen plugs expand
severely and actually create 	opens by lifting the devices. We have SEMs
of this.


I see this as an issue that is not going away and current solutions are
not entirely adequate. 

>	

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