Gary:
First a definition for the uninitiated:
"Popcorning" is the phenomenon that occurs when moisture is
absorbed by the plastic housing of the component (typically ICs and BGAs,
but also known to occur in plastic discretes and SMT connectors). This
causes the critical surfaces (e.g., die attach regions, any wire bonding
surface of the lead frame/die paddle, the top surface of the chip, etc.)
to delaminate.
(When this occurs the component package often resembles a piece of
popcorn, hence the name. Pat McCloskey at University of Maryland's CALCE
has a video that shows a component delaminating; it's interesting to see.)
The potential result is circuit failure of the component, either
immediately or over time. Emphasis on the word "potential"; Matt Doty at
Amkor and Willie Reynolds at Texas Instruments have significant amounts
of data indicating that there is no one-to-one correlation between part
delamination and part failure.
Component manufacturers that use IPC-SM-786A, JESD A112, or the about-
to-be-published joint IPC-JEDEC spec J-STD-020 are required by those
specs to specify a level (1-6) of part susceptibility to moisture.
Parts classified to level 1 may be stored outside in South Florida;
those classified to level 6 have a mandatory bake cycle, and then must be
reflowed within a period of time as specified by the component manufacturer.
Not surprisingly, most parts fall somewhere in-between. My own
unscientific surveys indicate that most assemblers store parts at level 2
or 3, with a few particularly sensitive parts stored at level 5.
The industry goal is to get all parts to level 2 by next year, which will
take some doing (improved materials, usually which come with higher costs) but
in my opinion is achievable. This would permit an assembler, for example,
to leave parts out (of bag or other medium such as a nitrogen storage
cabinet) for one year (!) at </=30C / 60%RH.
I don't have a copy of the spec in front of me (contact Doug Sandvick at
IPC for specifics), but can say that other measures besides baking are
possible. Try using moisture barrier bags packed with dessicant (this is
permissible for Levels 1-5; Level 6 is a mandatory bake) instead of
baking. There will be some costs associated with the bags and material,
of course, but then you'll probably avoid the downtime involved while
recalibrating the oven to 125C and baking the parts for 24 hours. (A
low temperature bake condition is permitted in the IPC spec--192 hours
(!!) at 40 +5/-0 C.)
Mike Buetow
IPC Communications Manager
2215 Sanders Road
Northbrook, IL 60062
P: 847-509-9700, ext. 335
F: 847-509-9798
[log in to unmask]
On Thu, 31 Oct 1996 [log in to unmask] wrote:
> Gary
>
> I believe that popcorning causes two failure modes,
> 1. damage to bond wires and other features, or
> 2. moisture condensation causes electrical failure.
>
> I believe that you have the latter case that's why baking cure the failure.
> However, the failure will re-occur once moisture permeate and condense
> again.
>
> Kuan-Shaur Lei
> Senior Member of Technical Staff
> Compaq Computer Corporation
> (713) 518-8099
> [log in to unmask]
> -------------
> Original Text
> >From [log in to unmask], on 10/30/96 6:36 PM:
> To: <[log in to unmask]>
>
> ------------------------------
>
> Content-Type: text/plain
>
> TechNet-d Digest Volume 96 : Issue 101
>
> Today's Topics:
> Re: DES and fab?? Back Pressure
> RE: pwb-cca : conformal coating
> DES, ASSY: Fine Pitch SMT
> RE: Relative issues concerning the tenting of vias -Reply
> ASSY: Passive Devices under PLCC-44
> FAB: Post-Lam Bake
> Re: Vision System
> Re[2]: pwb-cca : conformal coating
> RE: pwb-cca : conformal coating
> job posting
> bismuth based solder
> ASSY: GEN: Popcorning during reflow
>
> Administrivia:
> **********************************************************************
> ** IPC TechNet Digest List **
> **********************************************************************
>
> ------------------------------
>
> Date: Wed, 30 Oct 1996 14:08:08 -0500
> From: [log in to unmask] (Doug McKean)
> To: [log in to unmask]
> CC: [log in to unmask]
> Subject: Re: DES and fab?? Back Pressure
> Message-ID: <[log in to unmask]>
> Content-Type: text/plain; charset=us-ascii
> Content-Transfer-Encoding: 7bit
>
> [log in to unmask] wrote:
> > Has anybody heard of back pressure signaling??????
> > It has to do with electrical performance characteristics.
> > I do know that much.
> > Pweeze Halp?
> > Groovy
>
> GrooveMan,
>
> Don't know that much about it but here's an attempt...
>
> Has to do with "traffic control" in Ethernet (I think) to prevent
> congestion
> on the network. It's to prevent overloading in network nodes.
> Literally, electrical constipation.
>
> Back pressure signaling is used to notify a sending node to reduce its
> flow.
> A back pressure signal is sent 'upstream' to the first upstream node to
> slow
> the xmit speed to match the recieve speed of the first 'downstream' node on
> a net. This can obviously lead to all sorts of delays on a net.
>
> I 'think' this is what you're asking.
>
> Regards, Doug
>
> *******************************************************
> Doug McKean
> [log in to unmask]
> -------------------------------------------------------
> The comments and opinions stated herein are mine alone,
> and do not reflect those of my employer.
> -------------------------------------------------------
> *******************************************************
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
> ------------------------------
>
> Date: Wed, 30 Oct 1996 13:13:26 -0600
> From: [log in to unmask] (Mary Davis)
> To: [log in to unmask] (CINDY KEMP ORLANDO ISC *8-306-6),
> [log in to unmask] (Technet)
> Subject: RE: pwb-cca : conformal coating
> Message-ID: <[log in to unmask]>
> Content-Type: text/plain; charset="US-ASCII"
>
> Thought I would add my two cents on the subject.
>
> We are on a steep learning curve with respect to plastic parts. One of
> several problems we encountered was dewetting at conformal coat. After
> working the issue for a while, we have concluded that plastic parts are
> inherently harder to wet than other parts and that some conformal coating
> products are inherently better at wetting than others. A formula to
> predict wetting would be nice but we so far we have progressed by trial
> and error.
>
> The first coating that we tried was our
> 'good-old-stand-by-coat-anything', single component, solvent based,
> MIL-I-47058 UR. Wetting was spotty and unpredictable.
>
> We were also working with the manufacturer of our solvent based coating
> to evaluate their line of UV cure, single component, 100% solids,
> MIL-I-47058 coatings. We tried their 100% solids coatings on the plastic
> parts and had even less success. The dewetting of the plastic parts was a
> text book example of 'crawling' or 'retraction'. Wetting was good
> everywhere except on the plastic parts. Cleaning the plastic parts did
> not improve wetting.
>
>
> We then tried a Dymax product, a single component, 100% solids, UV cure,
> acrylic copolymer (meets AR, ER, and UR.) We had much better luck. So
> far this product coats plastic parts without a problem. It seems very
> robust with respect to plastic parts.
>
> Wetting is a function of the surface tension of the liquid and the free
> energy of the surface. If I understand the physics, wetting will not
> occur unless the surface tension of the liquid is less than the critical
> free energy of the solid. I assume that these parameters vary over a
> wide range for the materials in question - but there is very little data
> available. Even without the mold release variable, plastic is a low
> energy surface relative to metal and ceramic and, is therefore, more
> difficult to wet. I assume that solvent in a conformal coating improves
> wetting and, also, that the wetting characteristics of 100% solids
> products are greatly affected by the selection of monomers.
>
> Hope this information is of some help
>
> Mary Davis
> Sr. Material & Process Engineer
> Alliant Techsystems
> 206-356-3311
> [log in to unmask]
> ----------
> From: CINDY KEMP ORLANDO ISC *8-306-6[SMTP:[log in to unmask]]
> Sent: Wednesday, October 23, 1996 5:44 AM
> To: Technet
> Cc: GSPLASV
> Subject: FWD: pwb-cca : conformal coating
>
> Technet,
>
> I'm forwarding this from a colleague.
>
> Cindy Kemp
> Lockheed Martin
> Orlando, FL
> **************************************************************************
> *****
> *
>
> From: [log in to unmask]
> Date: Tue, 22 Oct 96 16:35:22 EDT
> Message-Id: <[log in to unmask]>
> To: [log in to unmask]
> Subject: pwb-cca : conformal coating
> Sender: [log in to unmask]
> Precedence: bulk
>
> hi group;
>
> We are finding that in designs using conformal coating (UR) over plastic
> parts
> that the cc is dewetting on the parts.
>
> Question - is this seen as a problem ?
>
> I am proposing that a note should be added to our designs as follows:
>
> CONFORMAL COAT DEWETTING ON PLASTIC ENCAPSULATED MICROCIRCUIT
> COMPONENT BODY IS ACCEPTABLE.
>
> If there is a better way please let me here from you.
>
> What is the real would doing ?
>
>
> thanx; Skip Greb
> ========================================================================
> To learn more about this email exploder (majordomo), including how to
> unsubscribe from this list, send e-mail to: [log in to unmask]
> and place the command "help" in the body of the message - subject may be
> left blank. Help can also be obtained on the WWW at
> http://www.epic.lmco.com/Majordomo
> ========================================================================
>
> **************************************************************************
> *
> * TechNet mail list is provided as a service by IPC using SmartList v3.05
> *
> **************************************************************************
> *
> * To unsubscribe from this list at any time, send a message to:
> *
> * [log in to unmask] with <subject: unsubscribe> and no text.
> *
> **************************************************************************
> *
>
>
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
> ------------------------------
>
> Date: Wed, 30 Oct 1996 11:26:12 -0800
> From: "John Parsons" <[log in to unmask]>
> To: "IPC TechNet" <[log in to unmask]>
> Subject: DES, ASSY: Fine Pitch SMT
> Message-Id: <[log in to unmask]>
> Content-Type: text/plain; charset=ISO-8859-1
> Content-Transfer-Encoding: 7bit
>
> A customer of ours has the following question(s):
>
> 1. We are currently working mostly on surface mount cards and a concern
> has arisen about solder flowing thru via's during the reflow process and
> shorting surface mount pads together as well as shorting vias's together.
> Via spec is currently 0.020 hole on a 0.040 pad.
>
> a) Does anyone seen this sort of problem associated particularily with
> 20mil pitch devices.
> b) If yes, does simply covering the vias with mask (LPI) eliminate this
> problem, or must the vias be "Capped".
>
> Any insight into this would be appreciated.
>
> Regards
> John Parsons
> Pre-Production Engineering
> Circuit Graphics Ltd.
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
> ------------------------------
>
> Date: Wed, 30 Oct 1996 11:53:04 -0800
> From: Bob Metcalf <[log in to unmask]>
> To: [log in to unmask], [log in to unmask]
> Subject: RE: Relative issues concerning the tenting of vias -Reply
> Message-Id: <[log in to unmask]>
>
> We have many customers who routinely use 50 micron dry film solder
> mask. We are even supplying some customers 25 micron dry film solder
> mask. The limiting factor is circuit height. Traditional pattern plating
> will
> often produce high conductors requiring additional mask thickness. In
> Japan the reason dry film mask works so well is for the most part they
> are panel plating with conductor heights usually not exceeding 50-60
> microns.
>
> The other thing to consider is application of the dry film solder mask. We
> have new applications that allow the mask to conform to circuitry more
> efficiently than traditional dry film solder mask. A 50 micron film can
> encapsulate what formally required a 100 micron dry film solder mask.
>
> Bob Metcalf
> Morton Electronic Materials
>
> >>> Goldman, Patricia J. <[log in to unmask]> 10/30/96 11:24am >>>
>
> Now, maybe I'm wrong here, but I do believe that 50 microns = 2 mils.
> That doesn't seem very thin to me.... The problem I believe with
> extremely thin dry films is usually pinholes and some sort of difficulty
> with the carrier.
> The other problem with a dry film solder mask is getting conformity over
> relatively high traces with a very thin film. You may hear from some df
> solder mask people on this one.
>
> There were some recent lengthy discussions on plugging vias. Best go
> to the web site and browse on that subject.
>
> Patty
> ----------
> From: TechNet-request
> To: TechNet
> Subject: Relative issues concerning the tenting of vias
> Date: Monday, October 28, 1996 11:12PM
>
> As the industry heads towards a point where surface mount technology
> and dense circuit topologies are the norm it becomes imperative to revisit
> the issue of to tent or not to tent.
> With liquid photoimageable solder masks still being an unreliable means of
> providing a uniformly conformal coating over copper features, is dry film
> the answer? Have strides been made of late in this technology which
> allay the inherent problems of process control, media thickness, and
> contamination due to oily residue buildup and its subsequent promise of
> sundry other problems such as delimitation? Has MIL SPEC 2000 (is rev
> C out yet?) acquiesced in the use of either the dry film or lpi tenting of
> vias as an acceptable practice?
> I have seen boards produced in the orient with dry film thicknesses as
> small as 50 microns. Are these available in the US or is their use
> shunned as being too thin? The suppliers I have spoken with cite
> minimum thicknesses in the >1 mil range. This lays bare other problems,
> such as potential tomb stoning while providing the opposite benefit of
> creating a solder well around SMT lands. The latter stated benefit is of
> dubious value if paste stencils and application coupled with fine tuned
> temperature control bogs down production and outweighs the reliability
> bonus, if any.
> It is a confusing issue and all the literature I can find seems to be
> horribly
> out of date (the latest being an excerpt from PC FAB magazine dated
> 1991. I am reasonably certain things have progressed since then, but
> where is the data?
> If you have any insights into this well masked dilemma, I for one could
> stand the relief. [log in to unmask]
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text.
> *
> ***************************************************************************
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text.
> *
> ***************************************************************************
>
>
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
> ------------------------------
>
> Date: Wed, 30 Oct 1996 13:25:31 -0600
> From: [log in to unmask]
> To: [log in to unmask]
> Subject: ASSY: Passive Devices under PLCC-44
> Message-ID: <[log in to unmask]>
> Content-Type: text/plain; charset=US-ASCII
> Content-Transfer-Encoding: 7bit
> Content-Description: cc:Mail note part
>
> Address,
>
> I asked this question once before but probably didn't send correctly.
> Is there anyone out there currently assembling chip resistors
> underneath a J-leaded PLCC-44? IPC-SM-782 does not spec the contact
> lead to package distance. I may be placing any of following 0603,
> 0805 and 0402 under the PLCC-44.
>
> Concerns I have:
>
> Without running a Thermal Profile with thermocouples will there be
> enough heat to reflow the underlying chip or will the PLCC-44 device
> rob it of heat?
>
> I'm I correct to assume the chip may crack should the pressure from
> the head be too strong and obviously if there is enough room under the
> device. The assembler does not have a variable pressure control for
> pick and place heads.
>
> And again is it feasible. I have other options but none that are as
> efficient as the one described.
>
> Please advise,
>
> John Gulley - QA
>
>
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
> ------------------------------
>
> Date: Wed, 30 Oct 96 14:10:58 MST
> From: [log in to unmask]
> To: [log in to unmask]
> Subject: FAB: Post-Lam Bake
> Message-Id: <[log in to unmask]>
>
> What is a typical cycle for baking FR4, rigid, multilayers after
> lamination?
> Why is this bake necessary?
>
> Any information would be greatly appreciated.
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
> ------------------------------
>
> Date: Wed, 30 Oct 96 09:38:41 PST
> From: "MohitGujral" <[log in to unmask]>
> To: [log in to unmask]
> Subject: Re: Vision System
> Message-Id: <[log in to unmask]>
>
> Hi Paresh....it depends how much u want to spend on a system like this,
> there are a lot of them out there....according do ur needs i would say
> try out
>
> 1> The theta group...seems to be a good machine....can do a bunch of stuff
> they have three models Vista, Verifier and Optima....all these m/c have
> the capability of real time SPC
> contact : ken Gribble
> 1 800 877 4874
>
> 2> The other company would be CR Technologies checks and verifies
> Component presence/Orientation/Correct part and a bunch of other stuff..
> Ph 714 448 0443
> Hope this helps...i don't work for them and the standard disclaimer
> applies....
>
> mohit gujral
>
> ______________________________ Reply Separator
> _________________________________
> Subject: Vision System
> Author: [log in to unmask] at uucpmail
> Date: 10/30/96 8:53 AM
>
> Good morning,
>
> We have a concern regarding potential of higher DPU at auto insertion
> when verifier is non-functional and operator loads one or more tubes of
> IC's or reels of components in the feeder. There is also a second
> related issue. Even when the verifier is working well, operator is
> required to do a TQC on the PCB's as final check at that operation.
> This TQC is very time consuming which in turns reduces productivity.
>
> I need your help in gaining knowledge and gathering information on any
> available vision system that would check for correct component in
> place. An efficient system should free us from worry when verifier is
> non-functional and increases productivity.
>
> Thanks for your help,
> Paresh Patel
> Oneac Corp.
> 847-816-6000 x-704.
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
> ------------------------------
>
> Date: Wed, 30 Oct 96 13:03:55
> From: "Lynch, Lyn" <[log in to unmask]>
> To: [log in to unmask] (CINDY KEMP ORLANDO ISC *8-306-6),
> [log in to unmask] (Technet), [log in to unmask]
> Subject: Re[2]: pwb-cca : conformal coating
> Message-Id: <[log in to unmask]>
>
> Here we go again. All polymers, including plastics used to encapsulate
> electronics, as well as all conformal coatings, have well documented
> moisture
> vapor transmission rates. So, it makes no practical difference if the body
> of
> the device is coated, or not. Although your customer amy demand complete
> coating
> of all surfaces on the board, if all exposed, conductive elements (leads
> and
> traces) are properly coated you will see no performance differences between
> boards with fully coated packages, and those with poorly coated packages.
> If, on the other hand, you rely on the coating to "stake" the device to the
> board, to reduce vibration induced stress, then the device should be clean
> and
> coated.
>
> By the way, if you are not dipping your boards in the conformal coating,
> I can assure you that you have uncoated surfaces somewhere on your board.
>
> The opinions stated herein are not necessarily those of my employer.
>
> Lyn R. Lynch
> 602.276.7361
> [log in to unmask]
> ______________________________ Reply Separator
> _________________________________
> Subject: RE: pwb-cca : conformal coating
> Author: [log in to unmask] at internet
> Date: 10/30/96 12:23 PM
>
>
> Thought I would add my two cents on the subject.
>
> We are on a steep learning curve with respect to plastic parts. One of
> several problems we encountered was dewetting at conformal coat. After
> working the issue for a while, we have concluded that plastic parts are
> inherently harder to wet than other parts and that some conformal coating
> products are inherently better at wetting than others. A formula to
> predict wetting would be nice but we so far we have progressed by trial
> and error.
>
> The first coating that we tried was our
> 'good-old-stand-by-coat-anything', single component, solvent based,
> MIL-I-47058 UR. Wetting was spotty and unpredictable.
>
> We were also working with the manufacturer of our solvent based coating
> to evaluate their line of UV cure, single component, 100% solids,
> MIL-I-47058 coatings. We tried their 100% solids coatings on the plastic
> parts and had even less success. The dewetting of the plastic parts was a
> text book example of 'crawling' or 'retraction'. Wetting was good
> everywhere except on the plastic parts. Cleaning the plastic parts did
> not improve wetting.
>
>
> We then tried a Dymax product, a single component, 100% solids, UV cure,
> acrylic copolymer (meets AR, ER, and UR.) We had much better luck. So
> far this product coats plastic parts without a problem. It seems very
> robust with respect to plastic parts.
>
> Wetting is a function of the surface tension of the liquid and the free
> energy of the surface. If I understand the physics, wetting will not
> occur unless the surface tension of the liquid is less than the critical
> free energy of the solid. I assume that these parameters vary over a
> wide range for the materials in question - but there is very little data
> available. Even without the mold release variable, plastic is a low
> energy surface relative to metal and ceramic and, is therefore, more
> difficult to wet. I assume that solvent in a conformal coating improves
> wetting and, also, that the wetting characteristics of 100% solids
> products are greatly affected by the selection of monomers.
>
> Hope this information is of some help
>
> Mary Davis
> Sr. Material & Process Engineer
> Alliant Techsystems
> 206-356-3311
> [log in to unmask]
> ----------
> From: CINDY KEMP ORLANDO ISC *8-306-6[SMTP:[log in to unmask]]
> Sent: Wednesday, October 23, 1996 5:44 AM
> To: Technet
> Cc: GSPLASV
> Subject: FWD: pwb-cca : conformal coating
>
> Technet,
>
> I'm forwarding this from a colleague.
>
> Cindy Kemp
> Lockheed Martin
> Orlando, FL
> **************************************************************************
> *****
> *
>
> From: [log in to unmask]
> Date: Tue, 22 Oct 96 16:35:22 EDT
> Message-Id: <[log in to unmask]>
> To: [log in to unmask]
> Subject: pwb-cca : conformal coating
> Sender: [log in to unmask]
> Precedence: bulk
>
> hi group;
>
> We are finding that in designs using conformal coating (UR) over plastic
> parts
> that the cc is dewetting on the parts.
>
> Question - is this seen as a problem ?
>
> I am proposing that a note should be added to our designs as follows:
>
> CONFORMAL COAT DEWETTING ON PLASTIC ENCAPSULATED MICROCIRCUIT
> COMPONENT BODY IS ACCEPTABLE.
>
> If there is a better way please let me here from you.
>
> What is the real would doing ?
>
>
> thanx; Skip Greb
> ========================================================================
> To learn more about this email exploder (majordomo), including how to
> unsubscribe from this list, send e-mail to: [log in to unmask]
> and place the command "help" in the body of the message - subject may be
> left blank. Help can also be obtained on the WWW at
> http://www.epic.lmco.com/Majordomo
> ========================================================================
>
> **************************************************************************
> *
> * TechNet mail list is provided as a service by IPC using SmartList v3.05
> *
> **************************************************************************
> *
> * To unsubscribe from this list at any time, send a message to:
> *
> * [log in to unmask] with <subject: unsubscribe> and no text.
> *
> **************************************************************************
> *
>
>
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
> ------------------------------
>
> Date: Wed, 30 Oct 1996 16:30:03 -0500
> From: [log in to unmask] (Howard Feldmesser)
> To: [log in to unmask] (Technet), [log in to unmask] (Mary Davis)
> Subject: RE: pwb-cca : conformal coating
> Message-Id: <[log in to unmask]>
> Content-Type: text/plain; charset="us-ascii"
> Content-Length: 956
>
> Technetters:
> I've been reading the mail about coating plastic parts with mostly
> a scientific curiosity type of interest level. Now the issue will smack me
> in the face as we try to coat PEMs for spacecraft use. We're planning to
> use Parylene to coat the assemblies for many reasons. Does anyone have any
> experience with Parylene on PEMs to help me along? I will share our
> results when I get some.
> Howard Feldmesser
> The Johns Hopkins University Applied Physics Laboratory
>
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
> ------------------------------
>
> Date: Wed, 30 Oct 96 16:42:00 CST
> From: "Schreiber, Carole" <[log in to unmask]>
> To: "[log in to unmask]" <[log in to unmask]>
> Subject: job posting
> Message-ID: <[log in to unmask]>
>
> Hi,
> I am a recruiter for Electronic Assembly Corporation in Neenah, WI and I
> have some open positions. How would I go about getting a job posted on
> the
> technet? What are the costs and all other details? We are a member of IPC.
> I would appreciate it if you could send me the details.
>
> I can be e-mailed at [log in to unmask]
>
> Thank you,
> Carole S.
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
> ------------------------------
>
> Date: Wed, 30 Oct 96 14:47:17 PST
> From: "Bob Bickers" <[log in to unmask]>
> To: [log in to unmask]
> Subject: bismuth based solder
> Message-Id: <[log in to unmask]>
>
> I have an assembly that requires a second solder process over a large
> area of the assembly, thus the need for a lower temp solder. I'm
> looking for the risks associated with the use of bismuth solder
> systems. Thanks in advance for your help.
>
> Bob Bickers
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
> ------------------------------
>
> Date: Wed, 30 Oct 1996 16:12:26 -0700
> From: [log in to unmask] (Gary Peterson)
> To: [log in to unmask]
> Subject: ASSY: GEN: Popcorning during reflow
> Message-Id: <[log in to unmask]>
>
> Has anyone else observed the following?
>
> We have a CMOS PQFP that was "popcorned" during reflow soldering. Cross
> sectioning clearly shows that the die, along with its mounting epoxy, has
> separated from the leadframe by approximately .002" (2-mils). There were
> no visible cracks in the plastic overmold material at 500X magnification.
>
> The problem is...some parts don't fail until after a few thermal cycles
> of 0 to 50 degrees C during live circuit testing at-speed. And...we can
> make them recover after failing by merely baking the entire board from
> 1.5 to 24 hours at 125 degrees C. The baking fix is not permanent and the
> parts eventually fail again. Some parts don't work initially but do work
> after the above baking treatment (we discovered, quite by accident, that
> baking
> "fixes" the parts).
>
>
> My question is...is the popcorning likely to be the only problem with
> these parts?
>
> Has anyone else been able to anneal a part so that it will recover from
> popcorning? Doesn't sound likely to me!
>
> Gary P.
> ---
> Gary D. Peterson
> _/_/_/ _/ _/ _/ SANDIA NATIONAL LABORATORIES _/_/_/
> _/ _/_/ _/ _/ P.O. Box 5800, M/S 0503 _/_/
> _/_/_/ _/ _/ _/ _/ Albuquerque, NM 87185-0503 _/_/_/_/_/_/
> _/ _/ _/_/ _/ Phone: (505)844-6980 _/ _/_/ _/
> _/_/_/ _/ _/ _/_/_/_/ FAX: (505)844-2925 _/ _/_/ _/
> E-Mail: [log in to unmask] _/_/_/
>
>
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
> --------------------------------
> End of TechNet-d Digest V96 Issue #101
> **************************************
>
> ***************************************************************************
> * TechNet mail list is provided as a service by IPC using SmartList v3.05 *
> ***************************************************************************
> * To unsubscribe from this list at any time, send a message to: *
> * [log in to unmask] with <subject: unsubscribe> and no text. *
> ***************************************************************************
>
>
***************************************************************************
* TechNet mail list is provided as a service by IPC using SmartList v3.05 *
***************************************************************************
* To unsubscribe from this list at any time, send a message to: *
* [log in to unmask] with <subject: unsubscribe> and no text. *
***************************************************************************
|
