At 08:47 AM 10/19/2005, Karl Sauter wrote:
>Dwight,
>
>How is heat to get from the device to the thermal via if you don't plate
>over it? Agree that CTE of the non-conductive fill must be a very close
>match.
See previous post. The via is still connected to the surface.
>Regards,
>Karl Sauter, Sun Microsystems
>
>
>Dwight Mattix wrote:
>>We have a lot of experience w/ this type failure. I'm working on the
>>assumption that there's a thermal via farm in that center gnd slug area.
>>A couple recommendations ff the cuff...
>> * Stay away from conductive via fill material whenever possible when
>>vias are tightly packed in "thermal via farms." Conductive fill is almost
>>never needed -- adds very little actual thermal/conductive benefit. We've
>>modeled it and test it. For my money, conductive fill is almost always a
>>waste of time and a real pain in the patootie from reliability standpoint.
>>The biggest benefit is that it's easier to plate over and get good copper
>>adhesion and that usually only matters on probe sites. Esp
>>evil/unpredictable in this application is CB100 (I've had lots of dialogue
>>w/ Dupont over the years on this type failure).
>> * Use a non-conductive fill that's more closely matched in CTE (e.g.San
>>eh) and don't overplate the fill.
>> * Arguably the most significant factor: don't plate over the thermal
>>vias. All overplating does is give the fill something to push against and
>>force the whole plated area up during thermal excursions. It's like
>>screwing a cylinder head on tightly and then pushing all the pistons up
>>against it (expanding fill at temp). Pop goes the weasel! Overplating
>>doesn't add any grounding or thermal benefit. The solder joint in the gnd
>>slug will still be fine w/ the dot pattern that emerges.
>> * As a work around/mod: We've eliminated a couple of these problems on
>>finished product by just etching or laser ablating a dot of copper off over
>>the fill.
>>
>>there's my $.02. Free and worth every penny. ;^)
>>
>>cheers,
>>dw
>>
>>At 07:29 AM 10/19/2005, Steve Gregory wrote:
>>
>>>Hi Wee Mei!
>>>
>>>I've got your pictures posted. Go to:
>>>
>>>http://www.stevezeva.homestead.com/files/U2_top.JPG
>>>http://www.stevezeva.homestead.com/files/U2_bottom.JPG
>>>http://www.stevezeva.homestead.com/files/U2_delamination.JPG
>>>
>>>Are the vias filled? Are you seeing this delamination on very many
>>>PCB's? Are you seeing it only on the bottom of the PCB?
>>>
>>>Kind regards,
>>>
>>>-Steve Gregory-
>>>Senior Process Engineer
>>>LaBarge Incorporated
>>>Tulsa, Oklahoma
>>>(918) 459-2285
>>>(918) 459-2350 FAX
>>>
>>>
>>>
>>>|---------+---------------------------->
>>>| | Wee Mei |
>>>| | <[log in to unmask]
>>>| | SG> |
>>>| | Sent by: TechNet |
>>>| | <[log in to unmask]>|
>>>| | |
>>>| | |
>>>| | 10/19/2005 03:47 |
>>>| | AM |
>>>| | Please respond to|
>>>| | TechNet E-Mail |
>>>| | Forum |
>>>| | <[log in to unmask]>|
>>>| | ; Please respond |
>>>| | to Wee Mei |
>>>| | <[log in to unmask]
>>>| | SG> |
>>>| | |
>>>|---------+---------------------------->
>>>
>>>
>>> >--------------------------------------------------------------------------------------------------------------|
>>>
>>> |
>>> |
>>> | To: [log in to unmask]@SMTP@Exchange
>>> |
>>> | cc: (bcc: Stephen R
>>>Gregory/LABARGE)
>>>|
>>> | Subject: [TN] Delamination at Thermal Via
>>>area? |
>>>
>>>
>>> >--------------------------------------------------------------------------------------------------------------|
>>>
>>>
>>>
>>>
>>>Hello,
>>>
>>>Just asked Steve to download 3 pictures on the defects. Kindly take a
>>>look
>>>at them and would appreciate some feedback on the possible root cause.
>>>
>>>Steve : Thanks for the downloading.
>>>
>>>Regards,
>>>Wee Mei
>>>
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