Bob,

I have seen serious cracking in tests on 1812 capacitors in -55 to +125C test.
They are a good bit smaller and the TCE mismatch not so bad so I am not at
all surprised at what you are seeing.

I would treat 1206's as the limit in kit that is going to see those sorts of
temperatures (-55) regularly in service, unless measures are taken to reduce
the problem.

David Whalley


>I have been looking at some 20 pin Leadless Ceramic Chip Carriers which have
>exhibited cracks. They are mounted on standard FR4 and thermal cycled between
>-55 +80 for 1000 hours.
>
>Cracking is a problem with this device as we know but not at these low lead
>counts. Many uses in their design rules make 28 pin devices the limit and then
>incorporate the use of matched substrate to reduce differential expansion.
>
>I would appreciate any feed back on failure that people have seen on testing of
>low lead count devices or even feed back on where people see the limit on pin
>count and the need for special substrates.

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