Hollandsworth, Ron wrote:
> 
>      no-clean fluxes and their affect on high speed switching,
>      rise and fall times, parasitic capacitance, leakage, affect
>      on resistance.
>      -Has the affect, if any, limited the flixibility of design
>       for top and bottom side CCAs?

	I'm no EE but have seen lots of parasitic-sensitive elec-
	tronics.

	I'll also confess I don't know much about how fluxes relate 		
with/through soldermask.

	Most parasitic sensitive situations in the digital realm are
	contained within very predictable stripline layers, where only
	subtractive etching is done and co-incidentally field effects
	are contained (high speed = low margins = high sensitivity).

	In analog (RF) and digital situations that require outer-layer
	(microstrip) constructions, traces are most often finished in
	bare copper with Soldermask protection.  This keeps added
	metallurgy from changing predicted performance; the consistency
	of tin/lead or even add'l copper plating can be an obstacle
	to achieving modeled structures.

	I know this doesn't answer the base question but it shows why I
	haven't faced this exact problem!

	Good luck, and best regards,
-- 
 
      Jeff Seeger                             Applied CAD Knowledge Inc
      Chief Technical Officer                      Tyngsboro, MA  01879
      [log in to unmask]                               508 649 9800

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