At 0.010" spacing, the 1000V potential drop for 1 minute test should not be 
performed in a humid
environment (above 70% RH) or on boards which have been stored in a humid 
environment.  There
is the potential for a subsurface failure mechanism, conductive anodic 
filament (CAF) formation to
occur.  This failure mechanism was first reported on for unprocessed FR-4 
boards in 1976 by
AT&T Bell Labs.
 ----------
>From: TCGE34A
>To: technet
>Subject: HI pot between surface features.
>Date: Wednesday, February 07, 1996 5:37AM
>
>-- [ From: Doug Jeffery * EMC.Ver #2.10P ] --
>
>
>Recently, I have been questioned about the use of a high pot test
>between two adjacent surface conductors.  What is the formula or rule
>for potential between adjacent conductors in air..uncoated, (no
>soldermask or confromal coat)?
>
>Do the same rules apply as between two parrellel planes internal in the
>board?
>
>Should I expect an .010" space to provide a withstanding voltage of
>1000 volts for 1 min.?
>
>Given the surface must be free of ionic contaminates...
>
>Thanks for the help..
>
>
>Doug Jeffery
>Electrotek
>[log in to unmask]
>
>
>
>