Jeff,

It all depends if you depanelize before or after assembly.  But it seems 
obvious you chose panelization to improve assembly efficientcy.  
However, you must investigate if the assemby will need a backup 
jig, due to card thicknesses, Type I assemblies (SMT 2 sides, typical 
for Smart cards), etc.  Route too much material away and not leave 
enough webbing (tab) and you minimize the rigidity of the array.  To 
improve this rigidity I recommend you score the card profiles versus 
routing.  Depanelize the completed assemblies by using a dual pizza 
cutter (Moetteller.....something like that) or similar(I can get the 
information at home).  Monitor the applied stresses with a 
strain gage and oscilloscope.  Typical Smart cards have components 
near card edges, due to realestate.  These components may be near 
the score path and could possibly induce solder joint fractures.  

You got the picture.  There's more to this, but I'll stop here.  Call 
if need more info

John Gulley 
Compuroute Inc.
Dallas, TX
214-340-0543
[log in to unmask]




> From:          "Baldwin, Jeff A" <[log in to unmask]>
> To:            TechNet <[log in to unmask]>
> Subject:       ASSY: PCMCIA Board Depanelizing
> Date:          Mon, 30 Sep 96 09:01:00 DST

> 
> Dear TechNet,
> 
> We are looking into setting up a PCMCIA assembly line.  We will probably 
> produce low to medium volumes.  What kind of depanelizing process would work 
> best?  We currently use a perforated tab method on regular boards.  Will 
> this method be acceptable for the thin PCMCIA  boards?
> 
> Thanks for your help.
> 
> Jeff Baldwin
> [log in to unmask]
> 
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