EE TIMES has several articles in this weeks newspaper (8-17-98)
on high speed interconnects.
Go to the Signals section
Excelent reference material for leading edge designs.

Article titles:

-Designers hone interconnect smarts
-Interconnect modeling breaks new ground
-Designers eye interconnect issues
-Gbit serial lines unsnarl backplane
-GTLP raises backplane performance
-Wide conductors cut microstrip loss
-Speed aggravates board crosstalk
-Timing errors haunt interconnects
-Simulation saves signal integrity

Raymond Smith
Sr. PWB Designer
Tellium
Oceanport, N.J.
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