I tried electrolytic tin in the early 80's and the tin slivers from plating overhang were a major contributor 
to reliability problems.  The etch factors for the chemistries able to produce solderable tin after etching 
could result in yield losses during board fabrication due to excessive plating overhang.  Slivers may escape 
detection at electrical test and result in a substandard separation between traces with a potential for 
dendritic growth (a sliver is present but doesn't contact the adjacent circuit).  I realize that you have a 
contact issue, but how can you be sure that the electrolytic tin plated contacts will not be prone to slivering 
when inserted into a customer's unit.  The question of how large of a sliver could you tolerate without 
affecting the operation of the unit must be answered when determining the amount of plating overhang that is 
acceptable.  I am not aware of the existance of a non-destructive test that will measure the amount of plating 
overhang.  This means either destructive testing or reliance on SPC and statistical analysis of your board 
fabricator's plating and etching processes.

Have you considered that tin is a melting metal and that this application will require solder resist over 
electroplated tin?  While employed at an OEM assembly operation undergoing the transition to surface mount, 
specifications permitted either tin/lead reflow or SMOBC/HAL.  We quickly found that solder resist dams, 
regardless of width, did not inhibit wicking of solder under the solder resist.  This resulted in a loss of 
solder volume and solder joints that were less than optimum.  A complicating factor was that the amount of 
wicking varied according to the geometry of the surrounding traces and the width of the dam.  This meant that 
each solder paste opening in the stencil would require optimization by experimentation.  It was much easier and 
more cost effective to require SMOBC/HAL as the finish.

I didn't mean to have this reply sound so negative, but as more questions arose the potential for reduced 
reliability seemed to increase.  I know that there have been proponents of tin as a replacement for precious 
metal plating, but the processes used to produce printed boards must be evaluated on thier own merits (and 
limitations).  I wish you luck with this project, and I hope that you will send me email to let me know the 
final results.

Don Vischulis
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_____________________________________________________________________________
[log in to unmask] wrote:
> 
> I want to evaluate the possibility of converting to a 100% tin electroplate
> finish on PCBs that requires a tin or tin-lead for contact pads.  Primarily
> 72 pin SIMM memory modules which are destined for use in tin or tin-lead
> (usually high tin content 90/10 - 95/5 tin-lead alloy).
> 
> Overall thickness is an issue with SIMM products (.050" + .004" -.003").  The
> HAL process results in a adequate finish most of the time, however this process
> can not be tightly controlled and is a root cause for thickness rejects and
> contact rel problems.
> 
> I've a couple of goals:
> 
> 1)  Improve quality and performance of our product by improving contact
>     reliability.
> 
> 2)  Give our PCB suppliers a way to improve yields for overall thickness.
> 
> There are other pluses (for us and the PCB suppliers) associated with a
> conversion to tin that I won't bring up.  I'm primarily concerned with
> overcoming any potential quality or reliability problems.  Here are some
> of my concerns:
> 
> 1)  Tin whisker growth.  Dependent on stress induced during electroplating.
>     Low/no stress plating is critical.  Whisker growth begins at ~50 'C.
>     Spacing between contact pads on a 72 pin SIMM is .010" so whisker growth
>     has to be eliminated.  Whiskering is not a problem with lead present.
> 
>     Test conditions:  High temperature storage, 150 'C unbiased.  Length ?
>                       1080 hrs 125 'C high temp operating life, biased.
>                       85/85 APB T&H
> 
> 2)  Tin undercut must be minimized to prevent tin slivers.
> 
> 3)  Solderability, tin-oxides form readily at room temperature.  This problem
>     exists with HAL, but to a lesser same extent.
> 
> 4)  Copper-tin intermetallic growth, tin should be a minimum of 200 microinches
>     thick.  Again, this problem exists with HAL.
> 
>     Test conditions: Same as in #1.
> 
> ************************************************************
> 
> My question is, has anyone experience with a tin electroplate finish in a
> similar application?  Any potential problems I've overlooked?
> 
> All comments are appreciated.  Thanks in advance.
> 
> Tracy Tennant   ([log in to unmask])
> 
> ph (208) 368-5963