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May 2003

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Subject:
Re: PCB_OPEN_VIAS_PROBLEMS
From:
Charles Caswell <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Mon, 19 May 2003 15:23:05 -0500
Content-Type:
text/plain
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text/plain (43 lines) 
In our case I have been told that the netlist testing is only done on one out of the lot. 
Charles

-----Original Message-----
From: Fineline Circuits, Inc. [mailto:[log in to unmask]]
Sent: Monday, May 19, 2003 4:26 PM
To: [log in to unmask]
Subject: Re: [TN] PCB_OPEN_VIAS_PROBLEMS


Wesley:
Weren't these boards tested by your board supplier? Electrical testing
should have failed the boards with the open vias . The vias may have voids
due to bad drilling and deburring which may clog the hole, poor smear
removal or malfunction of the electroless copper line-trapped air or could
be plating voids. Cross section of the open vias should pinpoint the
problem.

Sona
Fineline Circuits Inc.

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