Post was received, but not my area of expertise I'm afraid.

-----Original Message----- 
From: Wayne Thayer
Sent: Monday, April 15, 2019 2:45 PM
To: [log in to unmask]
Subject: Re: [TN] Solder mask chipping on board edge

I haven't received a single comment on this post. Was it held up by the
system or the moderator?

On Thu, Apr 11, 2019 at 5:58 PM Wayne Thayer <[log in to unmask]> wrote:

> Gentlemen-
>
> What the dickens is going on with IPC-A-600 Section 2.9.5? The
> "Nonconforming" snapshot at the bottom shows a bit of soldermask chipping
> due to the designer neglecting to clear the engraved area for the 
> "V-score"
> process. The chipped mask exposes no conductors and does not decrease the
> protected distance between any conductors. The edges of the through-hole
> pads are already exposed due to the soldermask backoff.
>
> I tried to work through the IPC requirements which should cover this case
> and I can't find any other than this explanatory picture book. The only
> explanatory statement is that this applies "when the design requires
> coverage to the printed board edge." Sounds like an unusual requirement 
> for
> this situation, given that a "V-score" makes a sloping, messy edge anyway.
>
> Is the convention that, because this silliness got into the document, if
> some lazy layout guy neglects to clear the path for the "V-score", that it
> is then presumed that "the design requires coverage to the printed board
> edge?" That'd be pretty ridiculous since if the lazy layout guy forgot to
> clear the mask, you can be certain they aren't going to bother creating a
> special note directing the fabricator to ignore his laziness.
>
> Wayne Thayer
>