David,

We are doing some work on electroless bumping of integrated circuits.
These devices are probed before our process and we are seeing some
problems associated with the damage due to probing, i.e. poor bump
flatness. Is your probing process applicable to ICs rather than
PCBs?

David Whalley
Manufacturing Engineering Department
Loughborough University
Loughborough
Leics LE11 3TU
UK

Tel. +44(0)1509 222930
Fax. +44(0)1509 267725

[log in to unmask]
http://www.lboro.ac.uk/departments/en/research/mp/david_whalley/index.html

At 08:20 AM 3/1/98 +0200, you wrote:
>Hello everyone,
>Being a new comer to this forum I have little experience as per how
>things are getting their answers.
>I am then resending this message that was sent a couple of days earlier.
>We develo a non contact electrical tester for baer board, and wish to
>get your input in the following matter.
>Bare board electrical testing system cause dents and damages to the
>tested pads by the pressure they apply by the testing pins.
>These dents often called witness marks can cause various difficulties
>during the assembly process in devices placement, soldering etc.
>I am looking for information regarding this matter:
>1. Are these damages causing problems at the assembly process? what
>kind?
>2. Are the damages affecting the assembly yield?
>3. If yes, is there any data about the % of savings at the assembly
>stage if these damages are avoided?
>4. Have the assebly people learn to live with these defects, overcoming
>the problems? what is the cost of such overoming? would elimination of
>these damages save money by avoiding to use these measures?
>5. Will a contactless bare board electrical test system, causing no
>damage at all will be an advantage to assembly people? in what sense?
>6. What would assembly people be will to do to push further such
>technology of bare board testing?
>David Banitt
>Exsight Ltd
>Israel

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