Dave:
     
     I believe that the designer would ensure that any vias used as test 
     points would not be tented in the first place.  This would have to be 
     defined in the soldermask Gerber layer.
     
     John R. Kretsch, P.E.
     Engineer, Design Assurance
     ADC Video Systems


______________________________ Reply Separator _________________________________
Subject: Re: FAB:  soldermask plugged vias
Author:  [log in to unmask] at internet-mail
Date:    07/23/96 16:25


     Dave,
     
     You can also have testability issues if you want to hit any vias when 
     you perform your ICT.  The test pins will hit the mask and not hit the 
     metal portion of the via.
     
     Roger Held
     Hitachi Computer Products (America), Inc.


______________________________ Reply Separator _________________________________
Subject: FAB:  soldermask plugged vias
Author:  [log in to unmask] at Internet-HICAM-OK
Date:    7/23/96 7:52 AM


Just curious:
     
We often have customers requesting that the (LPI) soldermask be 
screened/floodcoated to plug vias with soldermask.  I understand the 
reasons behind the design; however, I'm concerned about potential 
contaminates being trapped in the via, especially from the HAL or assembly 
process.  This soldermask process can produce vias that are partially to 
fully plugged from one (or both) sides of the PCB.  This can cause 
inadequate rinsing and cleaning of the vias during the HAL or assembly 
process.  
     
Any other ideas or concerns?  Has anyone looked at this issue in detail?
     
     
(This soldermask process can also produce exposed copper in the via, which 
has been discussed on this forum.  I believe the OSP surface finish would 
be a much safer choice with this via/soldermask design).
     
Thanks,
     
Dave Boggs
Merix Corporation
E-mail: [log in to unmask]
     
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