TECHNET Archives

August 2019

TechNet@IPC.ORG
Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
Re: TYPE III vs TYPE V vias
From:
Tan Geok Ang <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Tan Geok Ang <[log in to unmask]>
Date:
Wed, 28 Aug 2019 00:06:41 +0000
Content-Type:
text/plain
Parts/Attachments:
text/plain (15 lines) 
Especially on fine pitch and/or large area array I/O, due to PCB routing challenges or needs

________________________________

From: Stephen Pierce <[log in to unmask]>
Date: 28 August 2019 at 7:35:56 AM SGT
To: [log in to unmask] <[log in to unmask]>
Subject: Re: [TN] TYPE III vs TYPE V vias

Area array pad over a plated via (blind or through) is the most common reason

On Tue, Aug 27, 2019 at 3:49 PM Jack Olson <[log in to unmask]> wrote:
>
> When are caps on filled vias required by an application?

ATOM RSS1 RSS2