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January 2012

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Subject:
From:
Dwight Mattix <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Dwight Mattix <[log in to unmask]>
Date:
Tue, 17 Jan 2012 09:47:58 -0800
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Potato, Potahtoh.  Both are great tools and relate very closely to
one another.  Arguments about abound about the fine points of each by
pwb rel geeks (who? moi?)  Hard to beat your proximity to PWB Corp
and level of service. That'd make IST an easy choice for me.

At 09:32 AM 1/17/2012, Louis Hart wrote:
>Technetters, we are looking into possible changes in the
>electroplating process for printed circuit boards. Possible measures
>for the effect of changes on reliability of internal
>connections  under consideration are the 'Highly Accelerated Thermal
>Shock' and the 'IST' as in TM-650, 2.6.26.
>
>May I have some comments or guidance on the characteristics and
>merits of these two tests, or any others that we ought to consider?
>I leave it to your discretion, to determine if an off-line response
>is preferable than one to TechNet.
>
>Louis Hart
>Compunetics
>Monroeville, PA
>USA
>[log in to unmask]<mailto:[log in to unmask]>
>412-858-1232
>
>
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