Rick,

You have the right idea. Having a known layer with defects on it is the only way I know to 
physically check the accuracy of the automated inspection. If your using a reference logic system, Have the cam guys put in some "perfect" shorts and opens. You can also create dishdowns and virgin copper shorts ( short that are lower in profile than the actual circuit).

Ed Cosper

----------
From:  Rick Haynes[SMTP:[log in to unmask]]
Sent:  Friday, June 13, 1997 3:37 PM
To:  IPC TechNet
Cc:  Mark Cowling; Jim Reed; Michael C Heck; Robert A Carhart
Subject:  Automated Optical Inspection (AOI) of PCB inner layers

<<File: ATTRIBS.BND>><<File: ATT00001.txt>>I am looking for a person who has successfully developed a method to routinely
check the performance of an AOI used for PCB layers in order to gain some
guidance.

The goal is to verify the machine logic and detection capabilities daily/weekly
for SPC.  This is to head off a concern that the machine sensitivity may
degrade or just change with out our knowledge.  My thought is using a known
defective image which challenges the machine capability and then check to make
sure it provides a consistant rejection list.

Respectfully,  Rick Haynes


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