Jim I've etched innerlayers, pattern plated outerlayers and panel  plated
outerlayers.   You didn't specify which gives you grief.  They all have
their problems in manufacturing. 

Pattern plating is prevalent among board suppliers.  With pattern
plating, lines tend to be plated heavier where they are isolated and
thinner where grouped.  The thicker plating can mushroom over the
phorotesist and be very difficult to etch back down to the proper width.
 In this case the isolated lines are wider than expected.

Panel plating can be very uniform thickness accross the panel provided
the anode spacing and alignment are correct ahd the current density is
right.  Unfortunately, you must etch through 3 times as much copper on a
panel plated panel.    Isolated lines get much better solution movement
than grouped lines and tend to etch faster.  Over the years we have
tried using a variable artwork compensation to beef up the artwork line
width on isolated lines wider than grouped lines.   The case that fails
is  where a line starts in a group and then thins out.  (See my poor
ASCII sketch below.)

                 __________ 
                /		
-----------/
------------------------------
----------\
               \___________

In this case the line down through the center may be a full mil narrower
at the right end than the left end.    We haven't found a CAD program
smart enough to modify the center line properly.

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=====================


                 
On Fri, 26 Jul 96 09:35:00 PDT JIM ENNIS <[log in to unmask]> writes:
>
>We are having a significant problem with quickturn cards coming in 
>overetched, and we're trying to understand some things about the 
>process of 
>etching.
>     One question that has come up is:  Is it possible for etching to 
>be 
>greater in one area of the card over another? If so, how is this 
>possible, 
>and what are the design considerations for this?
>     Some here contend that every feature should etch down by the same 
>
>nominal amount, say .002 inch, whether the feature is an .008 trace or 
>a 
>large ground plane, since the whole PCB is exposed to etchant at the 
>same 
>time.  Is there fault in this thinking?
>     Thanks in advance.
>
>Jim Ennis
>Adtran Inc
>[log in to unmask]
>
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