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Date: | Wed, 29 Jan 97 07:20:44 cst |
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Hi Guenter -
I have always looked at the development of an empirical model that
predicts solder joint reliability in the electronics industry as one
of those after-the-fact dilemmas. Everyone has used solder as the
electrical and mechanical connection without thinking about the
material itself - it has always worked so why try to understand what
mechanisms are at work. Now that the electronics industry has pushed
the assembly pitchs down to .3mm (and lower!) the need to really
understand the deformation mechanisms occurring in solder are becoming
more critical. Lots of different opinions of the deformation
mechanisms are being suggested (e.g. Werner, Solomon, Lau, Frear,
Grossman) and with those resources dedicated to solving the problem
I'll bet a predictive formula that will have widespread industry
acceptance will emerge and be integrated into the design community.
I'm not a big Coffin-Manson equation fan because too many people try
to use the equation blindly without understanding how it applies. But
I do use the Coffin-Manson equation based on some stuff John Hagge has
published for first order estimates. When you complete your research
please publish the results so the rest of us can benefit.
Dave Hillman
Rockwell Collins
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Subject: Test temperature range
Author: [log in to unmask] at ccmgw1
Date: 1/29/97 6:21 AM
Hi Werner, Hi Dave
I think, if one performs accelerated tests on solder joints it is more
important not to activate a deformation mechanism which does not occur in
reality than stick to any temperature range. Tin lead solder deforms with
two different deformation mechanisms: Grainboundary sliding (GBs)and
dislocation climb (DC). Which deformation mechanism is activated depends on
the deformation rate ( temperature exchange rate ) and the temperature.
Grain boundary sliding is diffusion controlled and occurs at lower
deformation rates and at higher temperatures than dislocation climb. At
-40=B0C the strain rate activating primarily GBS is approx. 10E-6, at 125=
=B0C
approx. 10E-2. For a ceramic SMT capacitor 1210 on FR4 with a soldergap of
30um this results in temperature exchange rates of 0.1=B0C/min, and 500=B0C
/min respectively.
In performing accelerated testing with a Coffin- Mansion plot to perform a
lifetime prediction one must run temperature cycle tests with 2 or 3
different temperature ranges. In these test you shouldn't change the ratio
of GBS and DC to keep the Coffin Mansion exponent constant. Here lays the
rabbit in the pepper ( just a joke for those who know German ). It is not
easy to determine this ratio. We are working on it to prepare some diagrams
that bring all that theoretical stuff in a form easy to use. However,
measurements in automotive under hood electronics showed temperature
exchange rates of approx. 2=B0C/min. This induces mainly GBS at temperatures
around - 0=B0C. In office equippment we measured approx. 0.5=B0C/min. I thin=
k
for accelerated testing of the majority of electronic applications mainly
GBS can be assumed. In this case it might be wise to extend the temperature
range to higher temperatures (avoiding the glass transition temperature of
the board). If one extends the temperature range to lower temperatures use
1=B0C / min. from -20=B0C to -10=B0C, 2=B0C / min from -10=B0C to 0=B0C, 4=
=B0C / min.
from 0=B0C to 20=B0C and above 20=B0C as fast as your equipment runs.
Another point is the dwell time. At high temperatures ( 100=B0C ) 5 minutes
dwell time are enough to relieve all the stress induced. The lower the
temperatures the longer one must wait. At -20=B0C at least 30 min dwell time
are necessary, otherwise a lot of strain is stored elastically in the PCB
or in the leads of the IC's. It is questionable, whether one safes time if
the temperature range is extended to lower temperatures.
Best regards
Guenter Grossmann
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