I do not see on your list the first question that should be asked, why the 
small hole size in the first place?  On the 0.093 your aspect ratio( hole to 
thickness) is over 7and could be 9 depending on what size it is drilled at 
to get the finished 0.013.  Unless you have a supplier with bump or 
ultrasonics on the plating tank and electroless line you are creating a 
challenge for the solution to get through the holes and probably have a dog 
bone plating.  They pass electrical test because they probably do have an 
electrical connection at that time.  When you assembly and thermal shock the 
board at soldering the poor little barrel can not take the z asis expansion 
and lets go.  Don't blame the fabricator for this go talk to design.
When they are plated shut one always wonders what chemistry is along for the 
ride and will it cause premature failure later.
 ( Opinions are those of the author and not of his employer)
 ---------
From: [log in to unmask]
To: [log in to unmask]
Cc: [log in to unmask]
Subject: Open vias problem
Date: Friday, May 17, 1996 8:32AM

Hello,

We assemble circuit boards in a high product mix/low volume environment.
I'm uncomfortable about some PWB defects that were detected by our ATE
test equipment recently (i.e. testing of fully assembled/soldered circuit
board assemblies).  "Open" vias were detected in a few instances.  In other 
words, there wasn't continuity between the top side and bottom side
pads for the via.

For one particular part number we had 3 boards with an open via on each
out of 94 boards total.  The previous month we had 1 board out of 114
exhibit this problem.  This board is a .093" thick 4-layer SMOBC surface
mount board.

Another part number we experienced this problem with had an open via on
each of 3 out of 210 boards total.  This board is a .062" thick 6-layer
SMOBC surface mount board.

In both cases, the vias are specified to have a finished diameter of
0.013".  However, in both cases we've allowed them a minimum diameter
of 0 per their request (i.e. we won't reject any for vias plated shut).

Both of these part numbers are supposed to be 100% electrically tested
by the PWB supplier with a clamshell tester.  Therefore, ideally, I
would've expected zero instances of this type of problem.

QUESTIONS...

Is there anything wrong with allowing vias to plate shut?

Which PWB fabrication process(es) would cause an occasional open via?

Isn't it fair for me to expect their electrical test to detect these?

Should I be concerned about the via integrity in every board supplied
by this PWB fabricator, regardless of whether it passed our ATE test
or not?  (i.e. is this a sign of something far worse)

How would you proceed in this situation?

Please e-mail responses to [log in to unmask]  Thanks - any assistance
is appreciated.

Regards,

Mark Lettang