TECHNET Archives

March 1998

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
"Ryaby, John" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Tue, 17 Mar 1998 09:51:06 -0500
Content-Type:
text/plain
Parts/Attachments:
text/plain (26 lines)
I understand that the number of times that a printed circuit board is
exposed to the reflow process must be kept to a minimum.  I have never
seen, however,  information regarding the maximum number of times that a
board can be reflowed while maintaining solder joint/component
integrity.

A common practice, at my work location, is to expose board assemblies to
the reflow process in order to remove large components as the boards
exit the oven, while the solder is still liquidous.

In order to stop the above practice, I need some data to prove that this
practice is detrimental to PCB quality.   Does anyone have reliability
data regarding excessive reflow operations?

################################################################
TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c
################################################################
To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body:
To subscribe:   SUBSCRIBE TechNet <your full name>
To unsubscribe:   SIGNOFF TechNet 
################################################################
Please visit IPC web site (http://jefry.ipc.org/forum.htm) for additional information.
For the technical support contact Dmitriy Sklyar at [log in to unmask] or 847-509-9700 ext.311
################################################################


ATOM RSS1 RSS2