Mark Lettang asked:

>We assemble circuit boards in a high product mix/low volume environment.
>I'm uncomfortable about some PWB defects that were detected by our ATE
>test equipment recently (i.e. testing of fully assembled/soldered circuit
>board assemblies).  "Open" vias were detected in a few instances.  In
>other words, there wasn't continuity between the top side and bottom side
>pads for the via.
>
>For one particular part number we had 3 boards with an open via on each
>out of 94 boards total.  The previous month we had 1 board out of 114
>exhibit this problem.  This board is a .093" thick 4-layer SMOBC surface
>mount board.
>
>Another part number we experienced this problem with had an open via on
>each of 3 out of 210 boards total.  This board is a .062" thick 6-layer
>SMOBC surface mount board.
>
>In both cases, the vias are specified to have a finished diameter of
>0.013".  However, in both cases we've allowed them a minimum diameter
>of 0 per their request (i.e. we won't reject any for vias plated shut).
>
>Both of these part numbers are supposed to be 100% electrically tested
>by the PWB supplier with a clamshell tester.  Therefore, ideally, I
>would've expected zero instances of this type of problem.

This expectation may be unreasonable considering the thermal and mechanical
stresses of assembly and the lifetime reliability of the board.

>QUESTIONS...
>
>Is there anything wrong with allowing vias to plate shut?

Common practice, but somewhat risky, IMO. The fab vendor is worried that to
get good copper in the hole wall, some may plate shut or fill and fail to
clear at HASL.

>Which PWB fabrication process(es) would cause an occasional open via?

The worst areas are probably the low current density sections of the board
which tend to plate more slowly, and therefore have thin copper in the hole
walls. I would think that your prime risk is at reflow or wave solder
during assembly.

>Isn't it fair for me to expect their electrical test to detect these?

Yes, but perhaps they were continuous when they were tested as bare fabs.

>Should I be concerned about the via integrity in every board supplied
>by this PWB fabricator, regardless of whether it passed our ATE test
>or not?  (i.e. is this a sign of something far worse)

You have strong indications of poor copper integrity in the PTH walls. If
you have a vendor who can reliably plate these holes to a greater degree,
I'd sure say have only that vendor fab these boards.

>How would you proceed in this situation?

Especially on the 0.093" design, you are asking a lot to finish holes at
0.013". This is an aspect ratio of more than 7, on a thick board. Your
Z-axis expansion at reflow is greater than X or Y anyway, and it would tend
to crack week barrels.

During fab, these panels are probably being drilled at 0.018" in 2-up
stacks. It is probably costing you a premium regardless of the reliability
issue.

My recommendation would be go back to layout, increase the via diameters to
0.020" or more and make those via pads larger.

If you can't do that, have the vendor provide sections to show the copper
thickness in the holes. Most people ase for 0.001" minimum copper, but I'd
bet money you are not getting that much in the small vias.

You could do some thermal shock or "flex" testing on your assemblies to
confirm that you have more than a tenuous amount of copper in the vias, but
you might well see some fallout in doing this.

regards,

Jerry Cupples
Interphase Corporation
Dallas, TX USA
http://www.iphase.com/