Your question is a valid one No need to be appologetic. However the KGD
issue is only one facet of a more complex problem that must be viewed in
combination with the other issues. Perhaps the following will help you...
1) KDG means the die are tested (to some level) and (possibly) burned in.
Bare die are difficult to test and burn in and thus they tend to be a bit
pricey
compared to the pacakaged version of the same die (1 to 7X ). Key reasons
are: Each die has a different pad out thus test fixturing can get costly. As
for burn in, aluminum pads are most commonly used for bonding must be
contacted reliabily during burn in and then disengaged reliably without
damaging the bond pad. Methods to do this are often rather complicated
and can be rather expensive.
2) Bond pad arrangements and die size differ between die suppliers thus
many different board designs may be required. In short there are no
standard pinouts. If you are using chip and wire assembly you can be less
concerned about standards but may still run into die pin out incompatabilities
3)Bare chips do not avoid packaging, they simply make the board assembler
responsible for the wirebonding (or flip joining), encapsulation and test...
all the things you buy with a packaged die. It is just easier to do assembly
with
packaged die. Certain CSPs can, for instance, be placed using a chip shooter
at rates up to 20,000 uph.
Finally, in answer to your question 1... Yes, the packaging process is not
immune to losses in assembly of individual die but at least the entire board
assembly is not put at risk as is the case with all bare chip assembly because
rework and repair is much easier with packaged die.
Hope this helps...
Cheers!
J. Fjelstad
At 02:38 AM 12/8/97 -0800, you wrote:
>Having read November's CircuitTree, I seek the aid of few good, erudite
>TechNetters.
>
>Grant that I know nothing -- Please forgive my naive questions.
>
>The problem with direct chip attachment is seemingly defined as not
>having a known good die (KGD).
>
>1) When one is mounting a die on an interposer, would the interposer
>not face the same dilemma? In other words what does the interposer do
>to accomodate the absence of a known good die that the PCB could not?
>(One can see after attachment the features are scaled up for PCB
>attachment, though.)
>
>2) Where is the crux of the problem? Is it assembly or
>design/construction ability at the PCB stage?
>
>Tie Me, Fly Me, Whip Me, Flame Me for Asking
>Thanks,
>J. Warhelere
>
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