Testing spans over some variants. From nearly no testing at all to
expensive and time consuming. Example on the later is advanced microwave
semiconductors. You design the circuitry by means of a foundry software and
some other tools, you send the drawings to your foundry contact, who makes
the wafers you want, and you decide what to test. It's of course very
expensive. Not to mention SPACE semiconductors. I was responsible for the
assembly of packages for the ESA group, and before testing each chip
individually in special test stations, we had to wait for a guy from the ESA
organisation to come and inspect every chip visually. He had a doctors
degree and was a solid state guy with design and testing on top. He spent
days and weeks in the microscopy room and when he went back, we got the
wafers (on blue tape) . All chips that he didn't like were marked with a red
dot , which is recognized by the p-p as a reject.
/Inge
On 25 January 2011 16:34, Thayer, Wayne - IIW <[log in to unmask]> wrote:
> Hi Lars-
>
> We can always count on Joyce for the succinct answers! No wasted words!
>
> Almost always, a quick test is done at the wafer level and a map is created
> showing where the bad parts are. But the quick test is not complete--on
> Xilinx parts (and probably most FPGA's), most of the I/O remains unchecked.
> The whole testing process is done based on cost optimization--most defects
> are best caught at the wafer level (prior to investing in packaging), so
> they check for the most likely failures there. But it becomes expensive to
> get speed/voltage ratings at that level, so they wait until the unit is
> packaged to get those.
>
> Wayne
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Joyce Koo
> Sent: Tuesday, January 25, 2011 8:31 AM
> To: [log in to unmask]
> Subject: Re: [TN] TEST OF BARE DIE CIRCUITS
>
> Both.
> --------------------------
> Sent using BlackBerry
>
>
> ----- Original Message -----
> From: Lars Wallin [mailto:[log in to unmask]]
> Sent: Tuesday, January 25, 2011 08:22 AM
> To: [log in to unmask] <[log in to unmask]>
> Subject: [TN] TEST OF BARE DIE CIRCUITS
>
> Hello Technet,
>
> Can anyone short describe which sort of test methods are used for testing
> bare die circuits? Are they tested on the Waffer level or after cutting.
>
> Best Regards
> Lars Wallin
> IPC European Representative
> Location: Stockholm, Sweden
> Phone: +46 8 26 10 07
> Mobile: +46 70 212 74 39
> Email: [log in to unmask]<mailto:[log in to unmask]>
>
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